xref: /titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/hw_debug.h (revision f391a51a4e9639750045473dba1cc2831267c93e)
1 /*******************************************************************************
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  *
21  * Copyright 2014 QLogic Corporation
22  * The contents of this file are subject to the terms of the
23  * QLogic End User License (the "License").
24  * You may not use this file except in compliance with the License.
25  *
26  * You can obtain a copy of the License at
27  * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
28  * QLogic_End_User_Software_License.txt
29  * See the License for the specific language governing permissions
30  * and limitations under the License.
31  *
32  *
33  * Module Description:
34  *  This file defines the IDLE_CHK macros
35  *
36  * History:
37  *    11/02/08 Miri Shitrit    Inception.
38  ******************************************************************************/
39 
40 #ifndef _LM_DEBUG_H
41 #define _LM_DEBUG_H
42 
43 // bits must be corralted to the values in idle_chk.csv
44 #define IDLE_CHK_CHIP_MASK_57710     0x01
45 #define IDLE_CHK_CHIP_MASK_57711     0x02
46 #define IDLE_CHK_CHIP_MASK_57731     0x04
47 // Added for E3
48 #define IDLE_CHK_CHIP_MASK_57773     0x08
49 #define IDLE_CHK_CHIP_MASK_57773_B0  0x10
50 
51 enum {
52     IDLE_CHK_ERROR = 1,
53     IDLE_CHK_ERROR_NO_TRAFFIC, // indicates an error if test is not under traffic
54     IDLE_CHK_WARNING
55 } idle_chk_error_level;
56 
57 #if _MSC_VER
58 #if defined(_VBD_)
59 #include <ntddk.h>
60 #include <ntstrsafe.h>
61 #define snprintf RtlStringCchPrintfA
62 #define SNPRINTF_VAR(_str) sizeof(_str),
63 #else
64 #include "vc_os_emul.h"
65 #define SNPRINTF_VAR(_str) sizeof(_str), //needed due to change of sprintf_s to fix warnings
66 #endif // !NTDDI_VERSION
67 
68 
69 #else // !_MSC_VER
70 #define SNPRINTF_VAR(_str) sizeof(_str),
71 #endif // _MSC_VER
72 
73 #define CONDITION_CHK(condition, severity, fail_msg) \
74         total++; \
75         var_severity = severity; \
76         if (condition) { \
77             switch (var_severity) { \
78                 case IDLE_CHK_ERROR: \
79                     DbgMessage(pdev, FATAL, "idle_chk. Error   (level %d): %s\n", severity, fail_msg); \
80                     errors++; \
81                     break; \
82                 case IDLE_CHK_ERROR_NO_TRAFFIC: \
83                     DbgMessage(pdev, FATAL, "idle_chk. Error if no traffic (level %d):   %s\n", severity, fail_msg); \
84                     errors++; \
85                     break; \
86                 case IDLE_CHK_WARNING: \
87                     DbgMessage(pdev, WARN, "idle_chk. Warning (level %d): %s\n", severity, fail_msg); \
88                     warnings++; \
89                     break; \
90             }\
91         }
92 
93 
94 #define IDLE_CHK_CHIP_MASK_CHK(chip_mask) \
95         b_test_chip=0; \
96         var_chip_mask = 0; \
97         val = REG_RD(pdev, MISC_REG_CHIP_NUM); \
98         chip_rev = REG_RD(pdev, MISC_REG_CHIP_REV); \
99         chip_metal = REG_RD(pdev,  MISC_REG_CHIP_METAL); \
100         if (val == 5710) { \
101             var_chip_mask = IDLE_CHK_CHIP_MASK_57710; \
102         } else if (val == 5711 || val == 5712) { \
103             var_chip_mask = IDLE_CHK_CHIP_MASK_57711; \
104         } else if ((val == 5713) || (val == 5714) || (val == 5730) || (val == 5731))  { \
105             var_chip_mask =  IDLE_CHK_CHIP_MASK_57731; \
106         } else if (((chip_rev == 0xC) || (chip_rev == 0xD) || (chip_rev == 1)) && ((val == 5773) || (val == 5774) || (val == 5770))) { \
107             var_chip_mask =  IDLE_CHK_CHIP_MASK_57773_B0; \
108         } else if ((val == 5773) || (val == 5774) || (val == 5770)) { \
109             var_chip_mask =  IDLE_CHK_CHIP_MASK_57773; \
110         } \
111         if (var_chip_mask & chip_mask) { \
112             b_test_chip = 1;\
113         }
114 
115 /* read one reg and check the condition */
116 #define IDLE_CHK_1(chip_mask, offset, condition, severity, fail_msg) \
117         IDLE_CHK_CHIP_MASK_CHK(chip_mask); \
118         if (b_test_chip) { \
119             val = REG_RD(pdev, offset); \
120             snprintf (prnt_str, SNPRINTF_VAR(prnt_str) "%s. Value is 0x%x\n", fail_msg, val); \
121             val1 = 0; \
122             val2 = 0; \
123             CONDITION_CHK(condition, severity, prnt_str); \
124         }
125 
126 /* loop to read one reg and check the condition */
127 #define IDLE_CHK_2(chip_mask, offset, loop, inc, condition, severity, fail_msg) \
128         IDLE_CHK_CHIP_MASK_CHK(chip_mask); \
129         if (b_test_chip) { \
130             for (i = 0; i < (loop); i++) { \
131                 val = REG_RD(pdev, offset + i*(inc)); \
132                 snprintf (prnt_str, SNPRINTF_VAR(prnt_str) "%s. Value is 0x%x\n", fail_msg, val); \
133                 val1 = 0; \
134                 val2 = 0; \
135                 CONDITION_CHK(condition, severity, prnt_str); \
136             } \
137         }
138 
139 /* read two regs and check the condition */
140 #define IDLE_CHK_3(chip_mask, offset1, offset2, condition, severity, fail_msg) \
141          IDLE_CHK_CHIP_MASK_CHK(chip_mask); \
142          if (b_test_chip) { \
143             val1 = REG_RD(pdev, offset1); \
144             val2 = REG_RD(pdev, offset2); \
145             snprintf (prnt_str, SNPRINTF_VAR(prnt_str) "%s. Values are 0x%x 0x%x\n", fail_msg, val1, val2); \
146             val = 0; \
147             CONDITION_CHK(condition, severity, prnt_str); \
148          }
149 
150 /* read one reg and check according to CID_CAM */
151 #define IDLE_CHK_4(chip_mask, offset1, offset2, loop, inc, condition, severity, fail_msg) \
152         IDLE_CHK_CHIP_MASK_CHK(chip_mask); \
153         if (b_test_chip) { \
154             for (i = 0; i < (loop); i++) { \
155                 val1 = REG_RD(pdev, (offset1 + i*inc)); \
156                 val2 = REG_RD(pdev, (offset2 + i*(inc))); \
157                 val2 = val2 >> 1; \
158                 snprintf (prnt_str, SNPRINTF_VAR(prnt_str)  "%s LCID %d CID_CAM 0x%x. Value is 0x%x\n", fail_msg, i, val2, val1);\
159                 val = 0; \
160                 CONDITION_CHK(condition, severity, prnt_str); \
161             } \
162         }
163 
164 
165 /* read one reg and check according to another reg */
166 #define IDLE_CHK_5(chip_mask, offset, offset1, offset2, condition, severity, fail_msg) \
167         IDLE_CHK_CHIP_MASK_CHK(chip_mask); \
168         if (b_test_chip) { \
169             val = REG_RD(pdev, offset);\
170             if (!val) \
171                 IDLE_CHK_3(chip_mask, offset1, offset2, condition, severity, fail_msg); \
172         }
173 
174 /* read wide-bus reg and check sub-fields */
175 #define IDLE_CHK_6(chip_mask, offset, loop, inc, severity) \
176      { \
177         u32 rd_ptr, wr_ptr, rd_bank, wr_bank; \
178         IDLE_CHK_CHIP_MASK_CHK(chip_mask); \
179         if (b_test_chip) { \
180             for (i = 0; i < (loop); i++) { \
181                 val1 = REG_RD(pdev, offset + i*(inc)); \
182                 val2 = REG_RD(pdev, offset + i*(inc) + 4); \
183                 rd_ptr = ((val1 & 0x3FFFFFC0) >> 6); \
184                 wr_ptr = ((((val1 & 0xC0000000) >> 30) & 0x3) | ((val2 & 0x3FFFFF) << 2)); \
185                 snprintf (prnt_str, SNPRINTF_VAR(prnt_str) "QM: PTRTBL entry %d- rd_ptr is not equal to wr_ptr. Values are 0x%x 0x%x\n", i, rd_ptr, wr_ptr);\
186                 val = 0; \
187                 CONDITION_CHK((rd_ptr != wr_ptr), severity, prnt_str);\
188                 rd_bank = ((val1 & 0x30) >> 4); \
189                 wr_bank = (val1 & 0x03); \
190                 snprintf (prnt_str, SNPRINTF_VAR(prnt_str) "QM: PTRTBL entry %d- rd_bank is not equal to wr_bank. Values are 0x%x 0x%x\n", i, rd_bank, wr_bank); \
191                 val = 0; \
192                 CONDITION_CHK((rd_bank != wr_bank), severity, prnt_str); \
193             } \
194         } \
195       }
196 
197 
198 /* loop to read wide-bus reg and check according to another reg */
199 #define IDLE_CHK_7(chip_mask, offset, offset1, offset2, loop, inc, condition, severity, fail_msg) \
200     { \
201         u32_t chip_num; \
202         IDLE_CHK_CHIP_MASK_CHK(chip_mask); \
203         if (b_test_chip) { \
204             for (i = 0; i < (loop); i++) { \
205                 val = REG_RD(pdev, offset2 + i*4); \
206                 if ((val & 0x1) == 1) { \
207                     chip_num = REG_RD(pdev , MISC_REG_CHIP_NUM); \
208                     if ((chip_num == 0x1662) || (chip_num == 0x1663) || (chip_num == 0x1651) || (chip_num == 0x1652)) { \
209                         val1 = REG_RD(pdev, offset1 + i*(inc)); \
210                         val1 = REG_RD(pdev, offset1 + i*(inc) + 4); \
211                         val1 = REG_RD(pdev, offset1 + i*(inc) + 8); \
212                         REG_RD(pdev, offset1 + i*(inc) + 12); \
213                         val1 = (val1 & 0x1E000000) >> 25; \
214                     } else { \
215                         val1 = REG_RD(pdev, offset1 + i*(inc)); \
216                         val1 = REG_RD(pdev, offset1 + i*(inc) + 4); \
217                         val1 = REG_RD(pdev, offset1 + i*(inc) + 8); \
218                         REG_RD(pdev, offset1 + i*(inc) + 12); \
219                         val1 = (val1 & 0x00000078) >> 3; \
220                     } \
221                     val2 = REG_RD(pdev, offset + i*4); \
222                     snprintf (prnt_str, SNPRINTF_VAR(prnt_str) "%s - LCID %d CID_CAM 0x%x. Value is 0x%x\n", fail_msg, i, val2, val1); \
223                     CONDITION_CHK(condition, severity, prnt_str); \
224                 } \
225             } \
226         } \
227     }
228 
229 /* check PXP VQ occupancy according to condition */
230 #define IDLE_CHK_8(chip_mask, offset, condition, severity, fail_msg) \
231         IDLE_CHK_CHIP_MASK_CHK(chip_mask); \
232         if (b_test_chip) { \
233             val = REG_RD(pdev, offset); \
234             if (condition) { \
235                 snprintf (prnt_str, SNPRINTF_VAR(prnt_str)  "%s. Value is 0x%x\n%s\n", fail_msg, val,_vq_hoq(pdev,#offset)); \
236                 val = 0; \
237                 val1 = 0; \
238                 val2 = 0; \
239                 CONDITION_CHK(1, severity, prnt_str); \
240             } \
241         }
242 
243 #endif// _LM_DEBUG_H
244 
245