1 /***************************************************************** 2 * hw_debug.c 3 * 4 * CDDL HEADER START 5 * 6 * The contents of this file are subject to the terms of the 7 * Common Development and Distribution License (the "License"). 8 * You may not use this file except in compliance with the License. 9 * 10 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 11 * or http://www.opensolaris.org/os/licensing. 12 * See the License for the specific language governing permissions 13 * and limitations under the License. 14 * 15 * When distributing Covered Code, include this CDDL HEADER in each 16 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 * 23 * Copyright 2014 QLogic Corporation 24 * The contents of this file are subject to the terms of the 25 * QLogic End User License (the "License"). 26 * You may not use this file except in compliance with the License. 27 * 28 * You can obtain a copy of the License at 29 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/ 30 * QLogic_End_User_Software_License.txt 31 * See the License for the specific language governing permissions 32 * and limitations under the License. 33 * 34 * 35 * WARNING: DO NOT CHANGE THIS SCRIPT MANUALLY ! 36 * SCRIPT IS CREATED AUTOMATICALY VIA create_idle_chk.tcl 37 * 38 * Module Description: 39 * This code includes the idle_chk for WinDbg Extension (b10kd) 40 ******************************************************************/ 41 #if !defined(__LINUX) && !defined(__SunOS) && !defined(DOS) 42 #include <stdio.h> 43 #include <minmax.h> 44 #include <bcm_utils.h> 45 #endif 46 47 48 #ifdef __LINUX 49 #include <linux/string.h> 50 #endif 51 52 53 #include "hw_debug.h" 54 #include "lm5710.h" 55 #include "577xx_int_offsets.h" 56 #include "mm.h" 57 58 59 #ifdef _B10KD_EXT 60 #include "b10ext_redefs.h" 61 #include "b10ext.h" 62 #pragma warning( disable : 4242 4244 ) 63 #endif 64 65 // This procedure is used by idle_chk to disable timer scan at a given port 66 u32_t lm_disable_timer (struct _lm_device_t *pdev, u32_t port) { 67 u32_t val, i; 68 69 // On E2 disable timer of port 0 only 70 val = REG_RD(pdev, MISC_REG_CHIP_NUM); 71 if ((val == 5713) || (val == 5714) || (val == 5730) || (val == 5731)) { 72 port = 0; 73 } 74 75 // handle port 0 76 if (port == 0) { 77 val = REG_RD(pdev,TM_REG_EN_LINEAR0_TIMER); 78 if (val == 0) { 79 DbgMessage(pdev, INFORM, "idle_chk. lm_disable_timer(0) timer is not active\n"); 80 // timer not active 81 return 0; 82 } else { 83 // disable timer 84 REG_WR(pdev,TM_REG_EN_LINEAR0_TIMER, 0); 85 // poll until end of scan 86 for (i=0; i<200; i++) { 87 val = REG_RD(pdev,TM_REG_LIN0_SCAN_ON); 88 if (val == 0) { 89 DbgMessage(pdev, INFORM, "idle_chk. lm_disable_timer(0) timer is active\n"); 90 //scan completed - finish 91 return 1; 92 } 93 } 94 } 95 // handle port 1 96 } else if (port == 1) { 97 val = REG_RD(pdev,TM_REG_EN_LINEAR1_TIMER); 98 if (val == 0) { 99 DbgMessage(pdev, INFORM, "idle_chk. lm_disable_timer(1) timer is not active\n"); 100 // timer not active 101 return 0; 102 } else { 103 // disable timer 104 REG_WR(pdev,TM_REG_EN_LINEAR1_TIMER, 0); 105 // poll until end of scan 106 for (i=0; i<200; i++) { 107 val = REG_RD(pdev,TM_REG_LIN1_SCAN_ON); 108 if (val == 0) { 109 DbgMessage(pdev, INFORM, "idle_chk. lm_disable_timer(1) timer is active\n"); 110 //scan completed - finish 111 return 1; 112 } 113 } 114 } 115 } else { 116 DbgMessage(pdev, FATAL, "idle_chk. disable_timer() input port is unknown. Equal to %d\n",port); 117 return 0; 118 } 119 // if got here, timeout on timers scan has completed 120 DbgMessage(pdev, FATAL, "idle_chk. disable_timer(), timeout while waiting for timers scan to complete\n"); 121 return 1; 122 } 123 124 void lm_enable_timer (struct _lm_device_t *pdev, u32_t port) { 125 u32_t val; 126 127 // On E2 disable timer of port 0 only 128 val = REG_RD(pdev, MISC_REG_CHIP_NUM); 129 if ((val == 5713) || (val == 5714) || (val == 5730) || (val == 5731)) { 130 port = 0; 131 } 132 133 if (port == 0) { 134 REG_WR(pdev, TM_REG_EN_LINEAR0_TIMER,1); 135 } 136 else if (port == 1) { 137 REG_WR(pdev, TM_REG_EN_LINEAR1_TIMER,1); 138 } 139 } 140 141 lm_status_t lm_get_doorbell_info( 142 struct _lm_device_t *pdev) 143 { 144 u32_t val; 145 146 /* current DQ fill level */ 147 val = REG_RD(pdev,DORQ_REG_DQ_FILL_LVLF); 148 DbgMessage(pdev, FATAL, "lm_get_doorbell_info: DORQ current fill level=%d\n",val); 149 150 /* max DQ fill level */ 151 val = REG_RD(pdev,DORQ_REG_DQ_FILL_LVL_MAX); 152 DbgMessage(pdev, FATAL, "lm_get_doorbell_info: DORQ max fill level=%d\n",val); 153 154 /* doorbell discard cnt */ 155 val = REG_RD(pdev,DORQ_REG_DB_DIS_CNTR0); 156 DbgMessage(pdev, FATAL, "lm_get_doorbell_info: DORQ discard cnt=%d\n",val); 157 158 return LM_STATUS_SUCCESS; 159 } 160 161 static void _val2bits(IN u64_t val, IN u8_t nbits, OUT char *s) 162 { 163 int i; 164 165 DbgBreakIf(nbits > 64); 166 167 for(i = 0; i < nbits; ++i) { 168 if (val % 2 == 0) { 169 s[nbits-1-i] = '0'; 170 } else { 171 s[nbits-1-i] = '1'; 172 } 173 174 val = val >> 1; 175 } 176 } 177 178 static const char *_vq_hoq(struct _lm_device_t* pdev,IN const char *vq_regname) 179 { 180 static char hoq_msg[200]; 181 char func_desc[40]; 182 static const char* clients[] = {"USDM","CSDM","XSDM","TSDM","PBF","QM","Timers","Searcher", 183 "CDU_RD","DMAE","USDM_DP","HC","CDU_WR","DBG","_INVALID_","_INVALID_"}; 184 int vq = -1; 185 int i; 186 u32_t chip_num; 187 u32_t rd0,rd1,rd2,rd3; 188 u32_t req_id,len,addr_lo,addr_hi,done; 189 u32_t pfid,vfvalid,vfid,atc,client_id; 190 191 /* Only supported since E2 */ 192 chip_num = REG_RD(pdev,MISC_REG_CHIP_NUM); 193 if ((chip_num != 0x1662) && (chip_num != 0x1663) && (chip_num != 0x1651) && (chip_num != 0x1652)) { 194 return "-"; 195 } 196 197 /* Get VQ number from register name */ 198 if (!strncmp("PXP2_REG_RQ_VQ",vq_regname,14)) { 199 if (vq_regname[15] == '_') vq = (int)(vq_regname[14] - '0'); 200 else if (vq_regname[16] == '_') vq = (int)(10 * (vq_regname[14] - '0') + vq_regname[15] - '0'); 201 } 202 if ((vq <0) || (vq > 31)) { 203 snprintf(hoq_msg, SNPRINTF_VAR(hoq_msg) "Error: cannot get VQ # from register name %s",vq_regname); 204 return hoq_msg; 205 } 206 207 /* Read HOQ at specified VQ */ 208 REG_WR(pdev,PXP2_REG_RQ_HOQ_RAM_RD_REQ,vq); 209 for (i=0; i < 200; i++) { 210 if (REG_RD(pdev,PXP2_REG_RQ_HOQ_RAM_RD_STATUS)) break; 211 } 212 if (i == 200) { 213 return "Timeout waiting PXP2_REG_RQ_HOQ_RAM_RD_STATUS"; 214 } 215 216 /* Read Data */ 217 rd0 = REG_RD(pdev,PXP2_REG_RQ_HOQ_RAM_DATA_RD_0); 218 rd1 = REG_RD(pdev,PXP2_REG_RQ_HOQ_RAM_DATA_RD_1); 219 rd2 = REG_RD(pdev,PXP2_REG_RQ_HOQ_RAM_DATA_RD_2); 220 rd3 = REG_RD(pdev,PXP2_REG_RQ_HOQ_RAM_DATA_RD_3); 221 req_id = rd0 >> 16; 222 len = rd0 & 0xffff; 223 addr_lo = rd1; 224 addr_hi = rd2; 225 client_id = (rd3 >> 2) & 0xf; 226 done = (rd3 >> 6) & 1; 227 pfid = (rd3 >> 8) & 7; 228 vfvalid = (rd3 >> 11) & 1; 229 vfid = (rd3 >> 12) & 0x3f; 230 atc = (rd3 >> 18) & 0x7; 231 232 if (vfvalid) { 233 snprintf(func_desc, SNPRINTF_VAR(func_desc) "VFID %d (PF %d)",vfid,pfid); 234 } else { 235 snprintf(func_desc, SNPRINTF_VAR(func_desc) "PF %d",pfid); 236 } 237 snprintf(hoq_msg, SNPRINTF_VAR(hoq_msg) " Request at VQ%d is r/w %d bytes to/from address 0x%x_%08x by %s: rq_id=%d done=%d func=%s atc=%d.", 238 vq, len, addr_hi, addr_lo, clients[client_id], req_id, done, func_desc, atc); 239 return hoq_msg; 240 } 241 242 lm_status_t lm_get_storms_assert(struct _lm_device_t* pdev) 243 { 244 u8_t i,j; 245 char idx_str[9]; 246 char row_str[65]; 247 char last_idx=0; 248 #ifdef DBG 249 char *storm[] = { 250 "X", 251 "T", 252 "C", 253 "U" 254 }; 255 #endif 256 mm_mem_zero(idx_str, sizeof(idx_str)); 257 mm_mem_zero(row_str, sizeof(row_str)); 258 259 /* Go through all instances of all SEMIs */ 260 for (i = 0; i < 4; i++) { 261 DbgMessage(pdev, FATAL, "DATA %sSTORM_ASSERT_LIST_INDEX\n", storm[i]); 262 263 switch (i) { 264 case 0: 265 LM_INTMEM_READ8(pdev, XSTORM_ASSERT_LIST_INDEX_OFFSET, (u8_t*)&last_idx, BAR_XSTRORM_INTMEM); 266 break; 267 case 1: 268 LM_INTMEM_READ8(pdev, TSTORM_ASSERT_LIST_INDEX_OFFSET, (u8_t*)&last_idx, BAR_TSTRORM_INTMEM); 269 break; 270 case 2: 271 LM_INTMEM_READ8(pdev, CSTORM_ASSERT_LIST_INDEX_OFFSET, (u8_t*)&last_idx, BAR_CSTRORM_INTMEM); 272 break; 273 case 3: 274 LM_INTMEM_READ8(pdev, USTORM_ASSERT_LIST_INDEX_OFFSET, (u8_t*)&last_idx, BAR_USTRORM_INTMEM); 275 break; 276 default: 277 DbgBreak(); 278 } 279 280 _val2bits(last_idx, 8, idx_str); 281 DbgMessage(pdev, FATAL, "%s\n\n", idx_str); 282 283 /* print the asserts */ 284 #define STROM_ASSERT_ARRAY_SIZE 50 285 for (j = 0; j < STROM_ASSERT_ARRAY_SIZE; j++) { 286 u64_t row0=0, row1=0; 287 288 switch (i) { 289 case 0: 290 LM_INTMEM_READ64(pdev, XSTORM_ASSERT_LIST_OFFSET(j), &row0, BAR_XSTRORM_INTMEM); 291 LM_INTMEM_READ64(pdev, XSTORM_ASSERT_LIST_OFFSET(j) + 8, &row1, BAR_XSTRORM_INTMEM); 292 break; 293 case 1: 294 LM_INTMEM_READ64(pdev, TSTORM_ASSERT_LIST_OFFSET(j), &row0, BAR_TSTRORM_INTMEM); 295 LM_INTMEM_READ64(pdev, TSTORM_ASSERT_LIST_OFFSET(j) + 8, &row1, BAR_TSTRORM_INTMEM); 296 break; 297 case 2: 298 LM_INTMEM_READ64(pdev, CSTORM_ASSERT_LIST_OFFSET(j), &row0, BAR_CSTRORM_INTMEM); 299 LM_INTMEM_READ64(pdev, CSTORM_ASSERT_LIST_OFFSET(j) + 8, &row1, BAR_CSTRORM_INTMEM); 300 break; 301 case 3: 302 LM_INTMEM_READ64(pdev, USTORM_ASSERT_LIST_OFFSET(j), &row0, BAR_USTRORM_INTMEM); 303 LM_INTMEM_READ64(pdev, USTORM_ASSERT_LIST_OFFSET(j) + 8, &row1, BAR_USTRORM_INTMEM); 304 break; 305 default: 306 DbgBreak(); 307 } 308 309 // If the assert code is not invalid, print it. Otherwise break. 310 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 311 DbgMessage(pdev, FATAL, "DATA %sSTORM_ASSERT_INDEX\n", storm[i]); 312 _val2bits(j, 8, idx_str); 313 DbgMessage(pdev, FATAL, "%s\n", idx_str); 314 315 DbgMessage(pdev, FATAL, "DATA %sSTORM_ASSERT_ENTRY\n", storm[i]); 316 _val2bits(row0, 64, row_str); 317 DbgMessage(pdev, FATAL, "%s\n", row_str); 318 319 _val2bits(row1, 64, row_str); 320 DbgMessage(pdev, FATAL, "%s\n", row_str); 321 } else { 322 break; 323 } 324 } 325 } 326 327 return LM_STATUS_SUCCESS; 328 } 329 330 331 u32_t lm_idle_chk(struct _lm_device_t *pdev) { 332 #ifndef PXP2_REG_PXP2_INT_STS 333 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 334 #endif 335 u32_t i, val, val1, val2, chip_rev, chip_metal; 336 u32_t errors = 0; 337 u32_t warnings = 0; 338 u32_t total = 0; 339 u32_t is_enable_timer0, is_enable_timer1; 340 u8_t b_test_chip; 341 u8_t var_chip_mask = 0; //This variable is for eliminating a prefast warning 342 u8_t var_severity = 0; //This variable is for eliminating a prefast warning 343 char prnt_str[400]; 344 // Disable timer scans for port 0,1 345 is_enable_timer0 = lm_disable_timer(pdev, 0); 346 is_enable_timer1 = lm_disable_timer(pdev, 1); 347 // Read register 0x2114 val and check if condition on val exist 348 IDLE_CHK_1(0x3, 0x2114, ((val & 0x0FF010) != 0), IDLE_CHK_ERROR, "PCIE: ucorr_err_status is not 0"); 349 // Read register 0x2114 val and check if condition on val exist 350 IDLE_CHK_1(0x3, 0x2114, ((val & 0x100000) != 0), IDLE_CHK_WARNING, "PCIE: ucorr_err_status - Unsupported request error"); 351 // Read register 0x2120 val and check if condition on val exist 352 IDLE_CHK_1(0x3, 0x2120, (((val & 0x31C1) != 0x2000) && ((val & 0x31C1) != 0)), IDLE_CHK_WARNING, "PCIE: corr_err_status is not 0x2000"); 353 // Read register 0x2814 val and check if condition on val exist 354 IDLE_CHK_1(0x3, 0x2814, ((val & ~0x40100) != 0), IDLE_CHK_ERROR, "PCIE: attentions register is not 0x40100"); 355 // Read register 0x281c val and check if condition on val exist 356 IDLE_CHK_1(0x2, 0x281c, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR, "PCIE: attentions register is not 0x40040100"); 357 // Read register 0x2820 val and check if condition on val exist 358 IDLE_CHK_1(0x2, 0x2820, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR, "PCIE: attentions register is not 0x40040100"); 359 // Read register PXP2_REG_PGL_EXP_ROM2 val and check if condition on val exist 360 IDLE_CHK_1(0x3, PXP2_REG_PGL_EXP_ROM2, (val != 0xffffffff), IDLE_CHK_WARNING, "PXP2: There are outstanding read requests. Not all completios have arrived for read requests on tags that are marked with 0"); 361 // Read register 0x212c val in loop (incr by 4) and check if condition on val exist 362 IDLE_CHK_2(0x3, 0x212c, 4, 4, ((val != 0) && (errors > 0)), IDLE_CHK_WARNING, "PCIE: error packet header is not 0"); 363 // Read register 0x2104 val and check if condition on val exist 364 IDLE_CHK_1(0x1C, 0x2104, ((val & 0x0FD010) != 0), IDLE_CHK_ERROR, "PCIE: ucorr_err_status is not 0"); 365 // Read register 0x2104 val and check if condition on val exist 366 IDLE_CHK_1(0x1C, 0x2104, ((val & 0x100000) != 0), IDLE_CHK_WARNING, "PCIE: ucorr_err_status - Unsupported request error"); 367 // Read register 0x2104 val and check if condition on val exist 368 IDLE_CHK_1(0x1C, 0x2104, ((val & 0x2000) != 0), IDLE_CHK_WARNING, "PCIE: ucorr_err_status - Flow Control Protocol Error"); 369 // Read register 0x2110 val and check if condition on val exist 370 IDLE_CHK_1(0x1C, 0x2110, (((val & 0x31C1) != 0x2000) && ((val & 0x31C1) != 0)), IDLE_CHK_WARNING, "PCIE: corr_err_status is not 0x2000"); 371 // Read register 0x2814 val and check if condition on val exist 372 IDLE_CHK_1(0x1C, 0x2814, ((val & 0x2000000) != 0), IDLE_CHK_WARNING, "PCIE: TTX_BRIDGE_FORWARD_ERR - Received master request while BME was 0."); 373 // Read register 0x2814 val and check if condition on val exist 374 IDLE_CHK_1(0x1C, 0x2814, ((val & ~0x2040902) != 0), IDLE_CHK_ERROR, "PCIE: Func 0 1: attentions register is not 0x2040902"); 375 // Read register 0x2854 val and check if condition on val exist 376 IDLE_CHK_1(0x1C, 0x2854, ((val & ~0x10240902) != 0), IDLE_CHK_ERROR, "PCIE: Func 2 3 4: attentions register is not 0x10240902"); 377 // Read register 0x285c val and check if condition on val exist 378 IDLE_CHK_1(0x1C, 0x285c, ((val & ~0x10240902) != 0), IDLE_CHK_ERROR, "PCIE: Func 5 6 7: attentions register is not 0x10240902"); 379 // Read register 0x3040 val and check if condition on val exist 380 IDLE_CHK_1(0x18, 0x3040, ((val & 0x2) != 0), IDLE_CHK_ERROR, "PCIE: Overflow in DLP2TLP buffer"); 381 // Read register PXP2_REG_PGL_EXP_ROM2 val and check if condition on val exist 382 IDLE_CHK_1(0x1C, PXP2_REG_PGL_EXP_ROM2, (val != 0xffffffff), IDLE_CHK_WARNING, "PXP2: There are outstanding read requests for tags 0-31. Not all completios have arrived for read requests on tags that are marked with 0"); 383 // Read register 0x211c val in loop (incr by 4) and check if condition on val exist 384 IDLE_CHK_2(0x1C, 0x211c, 4, 4, ((val != 0) && (errors > 0)), IDLE_CHK_WARNING, "PCIE: error packet header is not 0"); 385 // Read register PGLUE_B_REG_INCORRECT_RCV_DETAILS val and check if condition on val exist 386 IDLE_CHK_1(0x1C, PGLUE_B_REG_INCORRECT_RCV_DETAILS, (val != 0), IDLE_CHK_ERROR, "PGLUE_B: Packet received from PCIe not according to the rules."); 387 // Read register PGLUE_B_REG_WAS_ERROR_VF_31_0 val and check if condition on val exist 388 IDLE_CHK_1(0x1C, PGLUE_B_REG_WAS_ERROR_VF_31_0, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: was_error for VFs 0-31 is not 0"); 389 // Read register PGLUE_B_REG_WAS_ERROR_VF_63_32 val and check if condition on val exist 390 IDLE_CHK_1(0x1C, PGLUE_B_REG_WAS_ERROR_VF_63_32, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: was_error for VFs 32-63 is not 0"); 391 // Read register PGLUE_B_REG_WAS_ERROR_VF_95_64 val and check if condition on val exist 392 IDLE_CHK_1(0x1C, PGLUE_B_REG_WAS_ERROR_VF_95_64, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: was_error for VFs 64-95 is not 0"); 393 // Read register PGLUE_B_REG_WAS_ERROR_VF_127_96 val and check if condition on val exist 394 IDLE_CHK_1(0x1C, PGLUE_B_REG_WAS_ERROR_VF_127_96, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: was_error for VFs 96-127 is not 0"); 395 // Read register PGLUE_B_REG_WAS_ERROR_PF_7_0 val and check if condition on val exist 396 IDLE_CHK_1(0x1C, PGLUE_B_REG_WAS_ERROR_PF_7_0, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: was_error for PFs 0-7 is not 0"); 397 // Read register PGLUE_B_REG_RX_ERR_DETAILS val and check if condition on val exist 398 IDLE_CHK_1(0x1C, PGLUE_B_REG_RX_ERR_DETAILS, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Completion received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Error code : 0 - Completion Timeout ; 1 - Unsupported Request; 2 - Completer Abort. (12) - valid bit."); 399 // Read register PGLUE_B_REG_RX_TCPL_ERR_DETAILS val and check if condition on val exist 400 IDLE_CHK_1(0x1C, PGLUE_B_REG_RX_TCPL_ERR_DETAILS, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: ATS TCPL received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Error code : 0 - Completion Timeout ; 1 - Unsupported Request; 2 - Completer Abort. (16:12) - OTB Entry ID. (17) - valid bit."); 401 // Read register PGLUE_B_REG_TX_ERR_WR_ADD_31_0 val and check if condition on val exist 402 IDLE_CHK_1(0x1C, PGLUE_B_REG_TX_ERR_WR_ADD_31_0, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Error in master write. Address(31:0) is not 0"); 403 // Read register PGLUE_B_REG_TX_ERR_WR_ADD_63_32 val and check if condition on val exist 404 IDLE_CHK_1(0x1C, PGLUE_B_REG_TX_ERR_WR_ADD_63_32, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Error in master write. Address(63:32) is not 0"); 405 // Read register PGLUE_B_REG_TX_ERR_WR_DETAILS val and check if condition on val exist 406 IDLE_CHK_1(0x1C, PGLUE_B_REG_TX_ERR_WR_DETAILS, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Error in master write. Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24) - VF_VALID. (30:25) - VFID."); 407 // Read register PGLUE_B_REG_TX_ERR_WR_DETAILS2 val and check if condition on val exist 408 IDLE_CHK_1(0x1C, PGLUE_B_REG_TX_ERR_WR_DETAILS2, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Error in master write. Error details 2nd register is not 0. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request."); 409 // Read register PGLUE_B_REG_TX_ERR_RD_ADD_31_0 val and check if condition on val exist 410 IDLE_CHK_1(0x1C, PGLUE_B_REG_TX_ERR_RD_ADD_31_0, (val != 0), IDLE_CHK_WARNING, "PGLUE: Error in master read address(31:0) is not 0"); 411 // Read register PGLUE_B_REG_TX_ERR_RD_ADD_63_32 val and check if condition on val exist 412 IDLE_CHK_1(0x1C, PGLUE_B_REG_TX_ERR_RD_ADD_63_32, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Error in master read address(63:32) is not 0"); 413 // Read register PGLUE_B_REG_TX_ERR_RD_DETAILS val and check if condition on val exist 414 IDLE_CHK_1(0x1C, PGLUE_B_REG_TX_ERR_RD_DETAILS, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Error in master read Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24) - VF_VALID. (30:25) - VFID."); 415 // Read register PGLUE_B_REG_TX_ERR_RD_DETAILS2 val and check if condition on val exist 416 IDLE_CHK_1(0x1C, PGLUE_B_REG_TX_ERR_RD_DETAILS2, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Error in master read Error details 2nd register is not 0. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request."); 417 // Read register PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS val and check if condition on val exist 418 IDLE_CHK_1(0x1C, PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Target VF length violation access."); 419 // Read register PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS val and check if condition on val exist 420 IDLE_CHK_1(0x1C, PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Target VF GRC space access failed permission check."); 421 // Read register PGLUE_B_REG_TAGS_63_32 val and check if condition on val exist 422 IDLE_CHK_1(0x1C, PGLUE_B_REG_TAGS_63_32, (val != 0xffffffff), IDLE_CHK_WARNING, "PGLUE_B: There are outstanding read requests for tags 32-63. Not all completios have arrived for read requests on tags that are marked with 0"); 423 // Read register PXP_REG_HST_VF_DISABLED_ERROR_VALID val1 and register PXP_REG_HST_VF_DISABLED_ERROR_DATA val2 and check if condition on val1,val2 exist 424 IDLE_CHK_3(0x1C, PXP_REG_HST_VF_DISABLED_ERROR_VALID, PXP_REG_HST_VF_DISABLED_ERROR_DATA, (val != 0), IDLE_CHK_WARNING, "PXP: Access to disabled VF took place"); 425 // Read register PXP_REG_HST_PER_VIOLATION_VALID val and check if condition on val exist 426 IDLE_CHK_1(0x1C, PXP_REG_HST_PER_VIOLATION_VALID, (val != 0), IDLE_CHK_WARNING, "PXP: Zone A permission violation occurred"); 427 // Read register PXP_REG_HST_INCORRECT_ACCESS_VALID val and check if condition on val exist 428 IDLE_CHK_1(0x1C, PXP_REG_HST_INCORRECT_ACCESS_VALID, (val != 0), IDLE_CHK_WARNING, "PXP: Incorrect transaction took place"); 429 // Read register PXP2_REG_RD_CPL_ERR_DETAILS val and check if condition on val exist 430 IDLE_CHK_1(0x1C, PXP2_REG_RD_CPL_ERR_DETAILS, (val != 0), IDLE_CHK_WARNING, "PXP2: Completion received with error. Error details register is not 0. (15:0) - ECHO. (28:16) - Sub Request length plus start_offset_2_0 minus 1."); 431 // Read register PXP2_REG_RD_CPL_ERR_DETAILS2 val and check if condition on val exist 432 IDLE_CHK_1(0x1C, PXP2_REG_RD_CPL_ERR_DETAILS2, (val != 0), IDLE_CHK_WARNING, "PXP2: Completion received with error. Error details 2nd register is not 0. (4:0) - VQ ID. (8:5) - client ID. (9) - valid bit."); 433 // Read register PXP2_REG_RQ_VQ0_ENTRY_CNT val and check if condition on val exist 434 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ0_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ0 is not empty"); 435 // Read register PXP2_REG_RQ_VQ1_ENTRY_CNT val and check if condition on val exist 436 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ1_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ1 is not empty"); 437 // Read register PXP2_REG_RQ_VQ2_ENTRY_CNT val and check if condition on val exist 438 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ2_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ2 is not empty"); 439 // Read register PXP2_REG_RQ_VQ3_ENTRY_CNT val and check if condition on val exist 440 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ3_ENTRY_CNT, (val > 2), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ3 is not empty"); 441 // Read register PXP2_REG_RQ_VQ4_ENTRY_CNT val and check if condition on val exist 442 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ4_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ4 is not empty"); 443 // Read register PXP2_REG_RQ_VQ5_ENTRY_CNT val and check if condition on val exist 444 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ5_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ5 is not empty"); 445 // Read register PXP2_REG_RQ_VQ6_ENTRY_CNT val and check if condition on val exist 446 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ6_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ6 is not empty"); 447 // Read register PXP2_REG_RQ_VQ7_ENTRY_CNT val and check if condition on val exist 448 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ7_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ7 is not empty"); 449 // Read register PXP2_REG_RQ_VQ8_ENTRY_CNT val and check if condition on val exist 450 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ8_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ8 is not empty"); 451 // Read register PXP2_REG_RQ_VQ9_ENTRY_CNT val and check if condition on val exist 452 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ9_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ9 is not empty"); 453 // Read register PXP2_REG_RQ_VQ10_ENTRY_CNT val and check if condition on val exist 454 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ10_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ10 is not empty"); 455 // Read register PXP2_REG_RQ_VQ11_ENTRY_CNT val and check if condition on val exist 456 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ11_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ11 is not empty"); 457 // Read register PXP2_REG_RQ_VQ12_ENTRY_CNT val and check if condition on val exist 458 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ12_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ12 is not empty"); 459 // Read register PXP2_REG_RQ_VQ13_ENTRY_CNT val and check if condition on val exist 460 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ13_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ13 is not empty"); 461 // Read register PXP2_REG_RQ_VQ14_ENTRY_CNT val and check if condition on val exist 462 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ14_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ14 is not empty"); 463 // Read register PXP2_REG_RQ_VQ15_ENTRY_CNT val and check if condition on val exist 464 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ15_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ15 is not empty"); 465 // Read register PXP2_REG_RQ_VQ16_ENTRY_CNT val and check if condition on val exist 466 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ16_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ16 is not empty"); 467 // Read register PXP2_REG_RQ_VQ17_ENTRY_CNT val and check if condition on val exist 468 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ17_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ17 is not empty"); 469 // Read register PXP2_REG_RQ_VQ18_ENTRY_CNT val and check if condition on val exist 470 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ18_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ18 is not empty"); 471 // Read register PXP2_REG_RQ_VQ19_ENTRY_CNT val and check if condition on val exist 472 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ19_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ19 is not empty"); 473 // Read register PXP2_REG_RQ_VQ20_ENTRY_CNT val and check if condition on val exist 474 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ20_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ20 is not empty"); 475 // Read register PXP2_REG_RQ_VQ21_ENTRY_CNT val and check if condition on val exist 476 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ21_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ21 is not empty"); 477 // Read register PXP2_REG_RQ_VQ22_ENTRY_CNT val and check if condition on val exist 478 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ22_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ22 is not empty"); 479 // Read register PXP2_REG_RQ_VQ23_ENTRY_CNT val and check if condition on val exist 480 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ23_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ23 is not empty"); 481 // Read register PXP2_REG_RQ_VQ24_ENTRY_CNT val and check if condition on val exist 482 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ24_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ24 is not empty"); 483 // Read register PXP2_REG_RQ_VQ25_ENTRY_CNT val and check if condition on val exist 484 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ25_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ25 is not empty"); 485 // Read register PXP2_REG_RQ_VQ26_ENTRY_CNT val and check if condition on val exist 486 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ26_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ26 is not empty"); 487 // Read register PXP2_REG_RQ_VQ27_ENTRY_CNT val and check if condition on val exist 488 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ27_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ27 is not empty"); 489 // Read register PXP2_REG_RQ_VQ28_ENTRY_CNT val and check if condition on val exist 490 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ28_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ28 is not empty"); 491 // Read register PXP2_REG_RQ_VQ29_ENTRY_CNT val and check if condition on val exist 492 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ29_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ29 is not empty"); 493 // Read register PXP2_REG_RQ_VQ30_ENTRY_CNT val and check if condition on val exist 494 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ30_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ30 is not empty"); 495 // Read register PXP2_REG_RQ_VQ31_ENTRY_CNT val and check if condition on val exist 496 IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ31_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ31 is not empty"); 497 // Read register PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY val and check if condition on val exist 498 IDLE_CHK_1(0x1F, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: rq_ufifo_num_of_entry is not 0"); 499 // Read register PXP2_REG_RQ_RBC_DONE val and check if condition on val exist 500 IDLE_CHK_1(0x1F, PXP2_REG_RQ_RBC_DONE, (val != 1), IDLE_CHK_ERROR, "PXP2: rq_rbc_done is not 1"); 501 // Read register PXP2_REG_RQ_CFG_DONE val and check if condition on val exist 502 IDLE_CHK_1(0x1F, PXP2_REG_RQ_CFG_DONE, (val != 1), IDLE_CHK_ERROR, "PXP2: rq_cfg_done is not 1"); 503 // Read register PXP2_REG_PSWRQ_BW_CREDIT val and check if condition on val exist 504 IDLE_CHK_1(0x3, PXP2_REG_PSWRQ_BW_CREDIT, (val != 0x1B), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: rq_read_credit and rq_write_credit are not 3"); 505 // Read register PXP2_REG_RD_START_INIT val and check if condition on val exist 506 IDLE_CHK_1(0x1F, PXP2_REG_RD_START_INIT, (val != 1), IDLE_CHK_ERROR, "PXP2: rd_start_init is not 1"); 507 // Read register PXP2_REG_RD_INIT_DONE val and check if condition on val exist 508 IDLE_CHK_1(0x1F, PXP2_REG_RD_INIT_DONE, (val != 1), IDLE_CHK_ERROR, "PXP2: rd_init_done is not 1"); 509 // Read register PXP2_REG_RD_SR_CNT val1 and register PXP2_REG_RD_SR_NUM_CFG val2 and check if condition on val1,val2 exist 510 IDLE_CHK_3(0x1F, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG, (val1 != (val2-1)), IDLE_CHK_WARNING, "PXP2: rd_sr_cnt is not equal to rd_sr_num_cfg"); 511 // Read register PXP2_REG_RD_BLK_CNT val1 and register PXP2_REG_RD_BLK_NUM_CFG val2 and check if condition on val1,val2 exist 512 IDLE_CHK_3(0x1F, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG, (val1 != val2), IDLE_CHK_WARNING, "PXP2: rd_blk_cnt is not equal to rd_blk_num_cfg"); 513 // Read register PXP2_REG_RD_SR_CNT val1 and register PXP2_REG_RD_SR_NUM_CFG val2 and check if condition on val1,val2 exist 514 IDLE_CHK_3(0x1F, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG, (val1 < (val2-3)), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: There are more than two unused SRs"); 515 // Read register PXP2_REG_RD_BLK_CNT val1 and register PXP2_REG_RD_BLK_NUM_CFG val2 and check if condition on val1,val2 exist 516 IDLE_CHK_3(0x1F, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG, (val1 < (val2-2)), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: There are more than two unused blocks"); 517 // Read register PXP2_REG_RD_PORT_IS_IDLE_0 val and check if condition on val exist 518 IDLE_CHK_1(0x1F, PXP2_REG_RD_PORT_IS_IDLE_0, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: P0 All delivery ports are not idle"); 519 // Read register PXP2_REG_RD_PORT_IS_IDLE_1 val and check if condition on val exist 520 IDLE_CHK_1(0x1F, PXP2_REG_RD_PORT_IS_IDLE_1, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: P1 All delivery ports are not idle"); 521 // Read register PXP2_REG_RD_ALMOST_FULL_0 val in loop (incr by 4) and check if condition on val exist 522 IDLE_CHK_2(0x1F, PXP2_REG_RD_ALMOST_FULL_0, 11, 4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: rd_almost_full is not 0"); 523 // Read register PXP2_REG_RD_DISABLE_INPUTS val and check if condition on val exist 524 IDLE_CHK_1(0x1F, PXP2_REG_RD_DISABLE_INPUTS , (val != 0), IDLE_CHK_ERROR, "PXP2: PSWRD inputs are disabled"); 525 // Read register PXP2_REG_HST_HEADER_FIFO_STATUS val and check if condition on val exist 526 IDLE_CHK_1(0x1F, PXP2_REG_HST_HEADER_FIFO_STATUS, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: HST header FIFO status is not 0"); 527 // Read register PXP2_REG_HST_DATA_FIFO_STATUS val and check if condition on val exist 528 IDLE_CHK_1(0x1F, PXP2_REG_HST_DATA_FIFO_STATUS, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: HST data FIFO status is not 0"); 529 // Read register PXP2_REG_PGL_WRITE_BLOCKED val and check if condition on val exist 530 IDLE_CHK_1(0x3, PXP2_REG_PGL_WRITE_BLOCKED, (val != 0), IDLE_CHK_ERROR, "PXP2: pgl_write_blocked is not 0"); 531 // Read register PXP2_REG_PGL_READ_BLOCKED val and check if condition on val exist 532 IDLE_CHK_1(0x3, PXP2_REG_PGL_READ_BLOCKED, (val != 0), IDLE_CHK_ERROR, "PXP2: pgl_read_blocked is not 0"); 533 // Read register PXP2_REG_PGL_WRITE_BLOCKED val and check if condition on val exist 534 IDLE_CHK_1(0x1C, PXP2_REG_PGL_WRITE_BLOCKED, (val != 0), IDLE_CHK_WARNING, "PXP2: pgl_write_blocked is not 0"); 535 // Read register PXP2_REG_PGL_READ_BLOCKED val and check if condition on val exist 536 IDLE_CHK_1(0x1C, PXP2_REG_PGL_READ_BLOCKED, (val != 0), IDLE_CHK_WARNING, "PXP2: pgl_read_blocked is not 0"); 537 // Read register PXP2_REG_PGL_TXW_CDTS val and check if condition on val exist 538 IDLE_CHK_1(0x1F, PXP2_REG_PGL_TXW_CDTS, (((val >> 17) & 1) != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: There is data which is ready"); 539 // Read register PXP_REG_HST_ARB_IS_IDLE val and check if condition on val exist 540 IDLE_CHK_1(0x1F, PXP_REG_HST_ARB_IS_IDLE, (val != 1), IDLE_CHK_WARNING, "PXP: HST arbiter is not idle"); 541 // Read register PXP_REG_HST_CLIENTS_WAITING_TO_ARB val and check if condition on val exist 542 IDLE_CHK_1(0x1F, PXP_REG_HST_CLIENTS_WAITING_TO_ARB, (val != 0), IDLE_CHK_WARNING, "PXP: HST one of the clients is waiting for delivery"); 543 // Read register PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS val and check if condition on val exist 544 IDLE_CHK_1(0x1E, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS, (val != 0), IDLE_CHK_WARNING, "PXP: HST Close the gates: Discarding internal writes"); 545 // Read register PXP_REG_HST_DISCARD_DOORBELLS_STATUS val and check if condition on val exist 546 IDLE_CHK_1(0x1E, PXP_REG_HST_DISCARD_DOORBELLS_STATUS, (val != 0), IDLE_CHK_WARNING, "PXP: HST Close the gates: Discarding doorbells"); 547 // Read register PXP2_REG_RQ_GARB val and check if condition on val exist 548 IDLE_CHK_1(0x1C, PXP2_REG_RQ_GARB, ((val & 0x1000) != 0), IDLE_CHK_WARNING, "PXP2: PSWRQ Close the gates is asserted. Check AEU AFTER_INVERT registers for parity errors."); 549 // Read register DMAE_REG_GO_C0 val and check if condition on val exist 550 IDLE_CHK_1(0x1F, DMAE_REG_GO_C0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 0 go is not 0"); 551 // Read register DMAE_REG_GO_C1 val and check if condition on val exist 552 IDLE_CHK_1(0x1F, DMAE_REG_GO_C1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 1 go is not 0"); 553 // Read register DMAE_REG_GO_C2 val and check if condition on val exist 554 IDLE_CHK_1(0x1F, DMAE_REG_GO_C2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 2 go is not 0"); 555 // Read register DMAE_REG_GO_C3 val and check if condition on val exist 556 IDLE_CHK_1(0x1F, DMAE_REG_GO_C3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 3 go is not 0"); 557 // Read register DMAE_REG_GO_C4 val and check if condition on val exist 558 IDLE_CHK_1(0x1F, DMAE_REG_GO_C4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 4 go is not 0"); 559 // Read register DMAE_REG_GO_C5 val and check if condition on val exist 560 IDLE_CHK_1(0x1F, DMAE_REG_GO_C5, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 5 go is not 0"); 561 // Read register DMAE_REG_GO_C6 val and check if condition on val exist 562 IDLE_CHK_1(0x1F, DMAE_REG_GO_C6, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 6 go is not 0"); 563 // Read register DMAE_REG_GO_C7 val and check if condition on val exist 564 IDLE_CHK_1(0x1F, DMAE_REG_GO_C7, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 7 go is not 0"); 565 // Read register DMAE_REG_GO_C8 val and check if condition on val exist 566 IDLE_CHK_1(0x1F, DMAE_REG_GO_C8, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 8 go is not 0"); 567 // Read register DMAE_REG_GO_C9 val and check if condition on val exist 568 IDLE_CHK_1(0x1F, DMAE_REG_GO_C9, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 9 go is not 0"); 569 // Read register DMAE_REG_GO_C10 val and check if condition on val exist 570 IDLE_CHK_1(0x1F, DMAE_REG_GO_C10, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 10 go is not 0"); 571 // Read register DMAE_REG_GO_C11 val and check if condition on val exist 572 IDLE_CHK_1(0x1F, DMAE_REG_GO_C11, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 11 go is not 0"); 573 // Read register DMAE_REG_GO_C12 val and check if condition on val exist 574 IDLE_CHK_1(0x1F, DMAE_REG_GO_C12, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 12 go is not 0"); 575 // Read register DMAE_REG_GO_C13 val and check if condition on val exist 576 IDLE_CHK_1(0x1F, DMAE_REG_GO_C13, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 13 go is not 0"); 577 // Read register DMAE_REG_GO_C14 val and check if condition on val exist 578 IDLE_CHK_1(0x1F, DMAE_REG_GO_C14, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 14 go is not 0"); 579 // Read register DMAE_REG_GO_C15 val and check if condition on val exist 580 IDLE_CHK_1(0x1F, DMAE_REG_GO_C15, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 15 go is not 0"); 581 // Read register CFC_REG_ERROR_VECTOR val and check if condition on val exist 582 IDLE_CHK_1(0x1F, CFC_REG_ERROR_VECTOR, (val != 0), IDLE_CHK_ERROR, "CFC: error vector is not 0"); 583 // Read register CFC_REG_NUM_LCIDS_ARRIVING val and check if condition on val exist 584 IDLE_CHK_1(0x1F, CFC_REG_NUM_LCIDS_ARRIVING, (val != 0), IDLE_CHK_ERROR, "CFC: number of arriving LCIDs is not 0"); 585 // Read register CFC_REG_NUM_LCIDS_ALLOC val and check if condition on val exist 586 IDLE_CHK_1(0x1F, CFC_REG_NUM_LCIDS_ALLOC, (val != 0), IDLE_CHK_ERROR, "CFC: number of alloc LCIDs is not 0"); 587 // Read register CFC_REG_NUM_LCIDS_LEAVING val and check if condition on val exist 588 IDLE_CHK_1(0x1F, CFC_REG_NUM_LCIDS_LEAVING, (val != 0), IDLE_CHK_ERROR, "CFC: number of leaving LCIDs is not 0"); 589 // Check if AC (ACTIVITY COUNTERS) value is allowed on this connection Type 590 IDLE_CHK_7(0x1F, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ((val1 == 0) && (val2 != 0) && (val2 != 2)), IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC is neither 0 nor 2 on connType 0 (ETH)"); 591 // Check if AC (ACTIVITY COUNTERS) value is allowed on this connection Type 592 IDLE_CHK_7(0x1F, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ((val1 == 1) && (val2 != 0)), IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC is not 0 on connType 1 (TOE)"); 593 // Check if AC (ACTIVITY COUNTERS) value is allowed on this connection Type 594 IDLE_CHK_7(0x1F, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ((val1 == 3) && (val2 != 0)), IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC is not 0 on connType 3 (iSCSI)"); 595 // Check if AC (ACTIVITY COUNTERS) value is allowed on this connection Type 596 IDLE_CHK_7(0x1F, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ((val1 == 4) && (val2 != 0)), IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC is not 0 on connType 4 (FCoE)"); 597 // Read register QM_REG_QTASKCTR_0 val in loop (incr by 4) and check if condition on val exist 598 IDLE_CHK_2(0x1F, QM_REG_QTASKCTR_0, 64, 4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Queue is not empty"); 599 // Read register QM_REG_VOQCREDIT_0 val1 and register QM_REG_VOQINITCREDIT_0 val2 and check if condition on val1,val2 exist 600 IDLE_CHK_3(0xF, QM_REG_VOQCREDIT_0, QM_REG_VOQINITCREDIT_0, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_0, VOQ credit is not equal to initial credit"); 601 // Read register QM_REG_VOQCREDIT_1 val1 and register QM_REG_VOQINITCREDIT_1 val2 and check if condition on val1,val2 exist 602 IDLE_CHK_3(0xF, QM_REG_VOQCREDIT_1, QM_REG_VOQINITCREDIT_1, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_1, VOQ credit is not equal to initial credit"); 603 // Read register QM_REG_VOQCREDIT_4 val1 and register QM_REG_VOQINITCREDIT_4 val2 and check if condition on val1,val2 exist 604 IDLE_CHK_3(0xF, QM_REG_VOQCREDIT_4, QM_REG_VOQINITCREDIT_4, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_4, VOQ credit is not equal to initial credit"); 605 // Read register QM_REG_PORT0BYTECRD val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 606 IDLE_CHK_3(0x3, QM_REG_PORT0BYTECRD, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: P0 Byte credit is not equal to initial credit"); 607 // Read register QM_REG_PORT1BYTECRD val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 608 IDLE_CHK_3(0x3, QM_REG_PORT1BYTECRD, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: P1 Byte credit is not equal to initial credit"); 609 // Read register CCM_REG_CAM_OCCUP val and check if condition on val exist 610 IDLE_CHK_1(0x1F, CCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: XX protection CAM is not empty"); 611 // Read register TCM_REG_CAM_OCCUP val and check if condition on val exist 612 IDLE_CHK_1(0x1F, TCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: XX protection CAM is not empty"); 613 // Read register UCM_REG_CAM_OCCUP val and check if condition on val exist 614 IDLE_CHK_1(0x1F, UCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: XX protection CAM is not empty"); 615 // Read register XCM_REG_CAM_OCCUP val and check if condition on val exist 616 IDLE_CHK_1(0x1F, XCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: XX protection CAM is not empty"); 617 // Read register BRB1_REG_NUM_OF_FULL_BLOCKS val and check if condition on val exist 618 IDLE_CHK_1(0x1F, BRB1_REG_NUM_OF_FULL_BLOCKS, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "BRB1: BRB is not empty"); 619 // Read register CSEM_REG_SLEEP_THREADS_VALID val and check if condition on val exist 620 IDLE_CHK_1(0x1F, CSEM_REG_SLEEP_THREADS_VALID, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: There are sleeping threads"); 621 // Read register TSEM_REG_SLEEP_THREADS_VALID val and check if condition on val exist 622 IDLE_CHK_1(0x1F, TSEM_REG_SLEEP_THREADS_VALID, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: There are sleeping threads"); 623 // Read register USEM_REG_SLEEP_THREADS_VALID val and check if condition on val exist 624 IDLE_CHK_1(0x1F, USEM_REG_SLEEP_THREADS_VALID, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: There are sleeping threads"); 625 // Read register XSEM_REG_SLEEP_THREADS_VALID val and check if condition on val exist 626 IDLE_CHK_1(0x1F, XSEM_REG_SLEEP_THREADS_VALID, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: There are sleeping threads"); 627 // Read register CSEM_REG_SLOW_EXT_STORE_EMPTY val and check if condition on val exist 628 IDLE_CHK_1(0x1F, CSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: External store FIFO is not empty"); 629 // Read register TSEM_REG_SLOW_EXT_STORE_EMPTY val and check if condition on val exist 630 IDLE_CHK_1(0x1F, TSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: External store FIFO is not empty"); 631 // Read register USEM_REG_SLOW_EXT_STORE_EMPTY val and check if condition on val exist 632 IDLE_CHK_1(0x1F, USEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: External store FIFO is not empty"); 633 // Read register XSEM_REG_SLOW_EXT_STORE_EMPTY val and check if condition on val exist 634 IDLE_CHK_1(0x1F, XSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: External store FIFO is not empty"); 635 // Read register CSDM_REG_SYNC_PARSER_EMPTY val and check if condition on val exist 636 IDLE_CHK_1(0x1F, CSDM_REG_SYNC_PARSER_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CSDM: Parser serial FIFO is not empty"); 637 // Read register TSDM_REG_SYNC_PARSER_EMPTY val and check if condition on val exist 638 IDLE_CHK_1(0x1F, TSDM_REG_SYNC_PARSER_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TSDM: Parser serial FIFO is not empty"); 639 // Read register USDM_REG_SYNC_PARSER_EMPTY val and check if condition on val exist 640 IDLE_CHK_1(0x1F, USDM_REG_SYNC_PARSER_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "USDM: Parser serial FIFO is not empty"); 641 // Read register XSDM_REG_SYNC_PARSER_EMPTY val and check if condition on val exist 642 IDLE_CHK_1(0x1F, XSDM_REG_SYNC_PARSER_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XSDM: Parser serial FIFO is not empty"); 643 // Read register CSDM_REG_SYNC_SYNC_EMPTY val and check if condition on val exist 644 IDLE_CHK_1(0x1F, CSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CSDM: Parser SYNC serial FIFO is not empty"); 645 // Read register TSDM_REG_SYNC_SYNC_EMPTY val and check if condition on val exist 646 IDLE_CHK_1(0x1F, TSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TSDM: Parser SYNC serial FIFO is not empty"); 647 // Read register USDM_REG_SYNC_SYNC_EMPTY val and check if condition on val exist 648 IDLE_CHK_1(0x1F, USDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "USDM: Parser SYNC serial FIFO is not empty"); 649 // Read register XSDM_REG_SYNC_SYNC_EMPTY val and check if condition on val exist 650 IDLE_CHK_1(0x1F, XSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XSDM: Parser SYNC serial FIFO is not empty"); 651 // Read register CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY val and check if condition on val exist 652 IDLE_CHK_1(0x1F, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block"); 653 // Read register TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY val and check if condition on val exist 654 IDLE_CHK_1(0x1F, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block"); 655 // Read register USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY val and check if condition on val exist 656 IDLE_CHK_1(0x1F, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "USDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block"); 657 // Read register XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY val and check if condition on val exist 658 IDLE_CHK_1(0x1F, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block"); 659 // Read register DORQ_REG_DQ_FILL_LVLF val and check if condition on val exist 660 IDLE_CHK_1(0x1F, DORQ_REG_DQ_FILL_LVLF, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DORQ: DORQ queue is not empty"); 661 // Read register CFC_REG_CFC_INT_STS val and check if condition on val exist 662 IDLE_CHK_1(0x1F, CFC_REG_CFC_INT_STS, (val != 0), IDLE_CHK_ERROR, "CFC: Interrupt status is not 0"); 663 // Read register CDU_REG_CDU_INT_STS val and check if condition on val exist 664 IDLE_CHK_1(0x1F, CDU_REG_CDU_INT_STS, (val != 0), IDLE_CHK_ERROR, "CDU: Interrupt status is not 0"); 665 // Read register CCM_REG_CCM_INT_STS val and check if condition on val exist 666 IDLE_CHK_1(0x1F, CCM_REG_CCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "CCM: Interrupt status is not 0"); 667 // Read register TCM_REG_TCM_INT_STS val and check if condition on val exist 668 IDLE_CHK_1(0x1F, TCM_REG_TCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "TCM: Interrupt status is not 0"); 669 // Read register UCM_REG_UCM_INT_STS val and check if condition on val exist 670 IDLE_CHK_1(0x1F, UCM_REG_UCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "UCM: Interrupt status is not 0"); 671 // Read register XCM_REG_XCM_INT_STS val and check if condition on val exist 672 IDLE_CHK_1(0x1F, XCM_REG_XCM_INT_STS, (val != 0), IDLE_CHK_ERROR, "XCM: Interrupt status is not 0"); 673 // Read register PBF_REG_PBF_INT_STS val and check if condition on val exist 674 IDLE_CHK_1(0xF, PBF_REG_PBF_INT_STS, (val != 0), IDLE_CHK_ERROR, "PBF: Interrupt status is not 0"); 675 // Read register TM_REG_TM_INT_STS val and check if condition on val exist 676 IDLE_CHK_1(0x1F, TM_REG_TM_INT_STS, (val != 0), IDLE_CHK_ERROR, "TIMERS: Interrupt status is not 0"); 677 // Read register DORQ_REG_DORQ_INT_STS val and check if condition on val exist 678 IDLE_CHK_1(0x1F, DORQ_REG_DORQ_INT_STS, (val != 0), IDLE_CHK_ERROR, "DORQ: Interrupt status is not 0"); 679 // Read register SRC_REG_SRC_INT_STS val and check if condition on val exist 680 IDLE_CHK_1(0x1F, SRC_REG_SRC_INT_STS, (val != 0), IDLE_CHK_ERROR, "SRCH: Interrupt status is not 0"); 681 // Read register PRS_REG_PRS_INT_STS val and check if condition on val exist 682 IDLE_CHK_1(0x1F, PRS_REG_PRS_INT_STS, (val != 0), IDLE_CHK_ERROR, "PRS: Interrupt status is not 0"); 683 // Read register BRB1_REG_BRB1_INT_STS val and check if condition on val exist 684 IDLE_CHK_1(0x1F, BRB1_REG_BRB1_INT_STS, ((val & ~0xFC00) != 0), IDLE_CHK_ERROR, "BRB1: Interrupt status is not 0"); 685 // Read register GRCBASE_XPB + PB_REG_PB_INT_STS val and check if condition on val exist 686 IDLE_CHK_1(0x1F, GRCBASE_XPB + PB_REG_PB_INT_STS, (val != 0), IDLE_CHK_ERROR, "XPB: Interrupt status is not 0"); 687 // Read register GRCBASE_UPB + PB_REG_PB_INT_STS val and check if condition on val exist 688 IDLE_CHK_1(0x1F, GRCBASE_UPB + PB_REG_PB_INT_STS, (val != 0), IDLE_CHK_ERROR, "UPB: Interrupt status is not 0"); 689 // Read register PXP2_REG_PXP2_INT_STS val and check if condition on val exist 690 IDLE_CHK_1(0x1, PXP2_REG_PXP2_INT_STS, (val != 0), IDLE_CHK_WARNING, "PXP2: Interrupt status 0 is not 0"); 691 // Read register PXP2_REG_PXP2_INT_STS_0 val and check if condition on val exist 692 IDLE_CHK_1(0x1E, PXP2_REG_PXP2_INT_STS_0, (val != 0), IDLE_CHK_WARNING, "PXP2: Interrupt status 0 is not 0"); 693 // Read register PXP2_REG_PXP2_INT_STS_1 val and check if condition on val exist 694 IDLE_CHK_1(0x1E, PXP2_REG_PXP2_INT_STS_1, (val != 0), IDLE_CHK_WARNING, "PXP2: Interrupt status 1 is not 0"); 695 // Read register QM_REG_QM_INT_STS val and check if condition on val exist 696 IDLE_CHK_1(0x1F, QM_REG_QM_INT_STS, (val != 0), IDLE_CHK_ERROR, "QM: Interrupt status is not 0"); 697 // Read register PXP_REG_PXP_INT_STS_0 val and check if condition on val exist 698 IDLE_CHK_1(0x1F, PXP_REG_PXP_INT_STS_0, (val != 0), IDLE_CHK_WARNING, "PXP: P0 Interrupt status is not 0"); 699 // Read register PXP_REG_PXP_INT_STS_1 val and check if condition on val exist 700 IDLE_CHK_1(0x1F, PXP_REG_PXP_INT_STS_1, (val != 0), IDLE_CHK_WARNING, "PXP: P1 Interrupt status is not 0"); 701 // Read register PGLUE_B_REG_PGLUE_B_INT_STS val and check if condition on val exist 702 IDLE_CHK_1(0x1C, PGLUE_B_REG_PGLUE_B_INT_STS, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: Interrupt status is not 0"); 703 // Read register DORQ_REG_RSPA_CRD_CNT val and check if condition on val exist 704 IDLE_CHK_1(0x1F, DORQ_REG_RSPA_CRD_CNT, (val != 2), IDLE_CHK_ERROR_NO_TRAFFIC, "DORQ: Credit to XCM is not full"); 705 // Read register DORQ_REG_RSPB_CRD_CNT val and check if condition on val exist 706 IDLE_CHK_1(0x1F, DORQ_REG_RSPB_CRD_CNT, (val != 2), IDLE_CHK_ERROR_NO_TRAFFIC, "DORQ: Credit to UCM is not full"); 707 // Read register QM_REG_VOQCRDERRREG val and check if condition on val exist 708 IDLE_CHK_1(0x3, QM_REG_VOQCRDERRREG, (val != 0), IDLE_CHK_ERROR, "QM: Credit error register is not 0 (byte or credit overflow/underflow)"); 709 // Read register DORQ_REG_DQ_FULL_ST val and check if condition on val exist 710 IDLE_CHK_1(0x1F, DORQ_REG_DQ_FULL_ST, (val != 0), IDLE_CHK_ERROR, "DORQ: DORQ queue is full"); 711 // Read register MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 val and check if condition on val exist 712 IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0, ((val & ~0xCFFC) != 0), IDLE_CHK_WARNING, "AEU: P0 AFTER_INVERT_1 is not 0"); 713 // Read register MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 val and check if condition on val exist 714 IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0, (val != 0), IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_2 is not 0"); 715 // Read register MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 val and check if condition on val exist 716 IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0, ((val & ~0xFFFF0000) != 0), IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_3 is not 0"); 717 // Read register MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 val and check if condition on val exist 718 IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, ((val & ~0x801FFFFF) != 0), IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_4 is not 0"); 719 // Read register MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 val and check if condition on val exist 720 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_1_FUNC_1, ((val & ~0xCFFC) != 0), IDLE_CHK_WARNING, "AEU: P1 AFTER_INVERT_1 is not 0"); 721 // Read register MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 val and check if condition on val exist 722 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1, (val != 0), IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_2 is not 0"); 723 // Read register MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 val and check if condition on val exist 724 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1, ((val & ~0xFFFF0000) != 0), IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_3 is not 0"); 725 // Read register MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 val and check if condition on val exist 726 IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, ((val & ~0x801FFFFF) != 0), IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_4 is not 0"); 727 // Read register MISC_REG_AEU_AFTER_INVERT_1_MCP val and check if condition on val exist 728 IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_1_MCP, ((val & ~0xCFFC) != 0), IDLE_CHK_WARNING, "AEU: MCP AFTER_INVERT_1 is not 0"); 729 // Read register MISC_REG_AEU_AFTER_INVERT_2_MCP val and check if condition on val exist 730 IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_2_MCP, (val != 0), IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_2 is not 0"); 731 // Read register MISC_REG_AEU_AFTER_INVERT_3_MCP val and check if condition on val exist 732 IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_3_MCP, ((val & ~0xFFFF0000) != 0), IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_3 is not 0"); 733 // Read register MISC_REG_AEU_AFTER_INVERT_4_MCP val and check if condition on val exist 734 IDLE_CHK_1(0x1F, MISC_REG_AEU_AFTER_INVERT_4_MCP, ((val & ~0x801FFFFF) != 0), IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_4 is not 0"); 735 // If register PBF_REG_DISABLE_NEW_TASK_PROC_P0 is valid, read PBF_REG_P0_CREDIT val1 and register PBF_REG_P0_INIT_CRD val2 and check if codition on val1,val2 exist 736 IDLE_CHK_5(0xF, PBF_REG_DISABLE_NEW_TASK_PROC_P0, PBF_REG_P0_CREDIT, PBF_REG_P0_INIT_CRD, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P0 credit is not equal to init_crd"); 737 // If register PBF_REG_DISABLE_NEW_TASK_PROC_P1 is valid, read PBF_REG_P1_CREDIT val1 and register PBF_REG_P1_INIT_CRD val2 and check if codition on val1,val2 exist 738 IDLE_CHK_5(0xF, PBF_REG_DISABLE_NEW_TASK_PROC_P1, PBF_REG_P1_CREDIT, PBF_REG_P1_INIT_CRD, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P1 credit is not equal to init_crd"); 739 // Read register PBF_REG_P4_CREDIT val1 and register PBF_REG_P4_INIT_CRD val2 and check if condition on val1,val2 exist 740 IDLE_CHK_3(0xF, PBF_REG_P4_CREDIT, PBF_REG_P4_INIT_CRD, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P4 credit is not equal to init_crd"); 741 // If register PBF_REG_DISABLE_NEW_TASK_PROC_Q0 is valid, read PBF_REG_CREDIT_Q0 val1 and register PBF_REG_INIT_CRD_Q0 val2 and check if codition on val1,val2 exist 742 IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q0, PBF_REG_CREDIT_Q0, PBF_REG_INIT_CRD_Q0, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q0 credit is not equal to init_crd"); 743 // If register PBF_REG_DISABLE_NEW_TASK_PROC_Q1 is valid, read PBF_REG_CREDIT_Q1 val1 and register PBF_REG_INIT_CRD_Q1 val2 and check if codition on val1,val2 exist 744 IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q1, PBF_REG_CREDIT_Q1, PBF_REG_INIT_CRD_Q1, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q1 credit is not equal to init_crd"); 745 // If register PBF_REG_DISABLE_NEW_TASK_PROC_Q2 is valid, read PBF_REG_CREDIT_Q2 val1 and register PBF_REG_INIT_CRD_Q2 val2 and check if codition on val1,val2 exist 746 IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q2, PBF_REG_CREDIT_Q2, PBF_REG_INIT_CRD_Q2, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q2 credit is not equal to init_crd"); 747 // If register PBF_REG_DISABLE_NEW_TASK_PROC_Q3 is valid, read PBF_REG_CREDIT_Q3 val1 and register PBF_REG_INIT_CRD_Q3 val2 and check if codition on val1,val2 exist 748 IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q3, PBF_REG_CREDIT_Q3, PBF_REG_INIT_CRD_Q3, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q3 credit is not equal to init_crd"); 749 // If register PBF_REG_DISABLE_NEW_TASK_PROC_Q4 is valid, read PBF_REG_CREDIT_Q4 val1 and register PBF_REG_INIT_CRD_Q4 val2 and check if codition on val1,val2 exist 750 IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q4, PBF_REG_CREDIT_Q4, PBF_REG_INIT_CRD_Q4, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q4 credit is not equal to init_crd"); 751 // If register PBF_REG_DISABLE_NEW_TASK_PROC_Q5 is valid, read PBF_REG_CREDIT_Q5 val1 and register PBF_REG_INIT_CRD_Q5 val2 and check if codition on val1,val2 exist 752 IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q5, PBF_REG_CREDIT_Q5, PBF_REG_INIT_CRD_Q5, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q5 credit is not equal to init_crd"); 753 // Read register PBF_REG_CREDIT_LB_Q val1 and register PBF_REG_INIT_CRD_LB_Q val2 and check if condition on val1,val2 exist 754 IDLE_CHK_3(0x10, PBF_REG_CREDIT_LB_Q, PBF_REG_INIT_CRD_LB_Q, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: LB Q credit is not equal to init_crd"); 755 // Read register PBF_REG_P0_TASK_CNT val and check if condition on val exist 756 IDLE_CHK_1(0xF, PBF_REG_P0_TASK_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P0 task_cnt is not 0"); 757 // Read register PBF_REG_P1_TASK_CNT val and check if condition on val exist 758 IDLE_CHK_1(0xF, PBF_REG_P1_TASK_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P1 task_cnt is not 0"); 759 // Read register PBF_REG_P4_TASK_CNT val and check if condition on val exist 760 IDLE_CHK_1(0xF, PBF_REG_P4_TASK_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P4 task_cnt is not 0"); 761 // Read register PBF_REG_TASK_CNT_Q0 val and check if condition on val exist 762 IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q0 task_cnt is not 0"); 763 // Read register PBF_REG_TASK_CNT_Q1 val and check if condition on val exist 764 IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q1 task_cnt is not 0"); 765 // Read register PBF_REG_TASK_CNT_Q2 val and check if condition on val exist 766 IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q2 task_cnt is not 0"); 767 // Read register PBF_REG_TASK_CNT_Q3 val and check if condition on val exist 768 IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q3 task_cnt is not 0"); 769 // Read register PBF_REG_TASK_CNT_Q4 val and check if condition on val exist 770 IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q4 task_cnt is not 0"); 771 // Read register PBF_REG_TASK_CNT_Q5 val and check if condition on val exist 772 IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q5, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q5 task_cnt is not 0"); 773 // Read register PBF_REG_TASK_CNT_LB_Q val and check if condition on val exist 774 IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_LB_Q, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: LB Q task_cnt is not 0"); 775 // Read register XCM_REG_CFC_INIT_CRD val and check if condition on val exist 776 IDLE_CHK_1(0x1F, XCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: CFC_INIT_CRD is not 1"); 777 // Read register UCM_REG_CFC_INIT_CRD val and check if condition on val exist 778 IDLE_CHK_1(0x1F, UCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: CFC_INIT_CRD is not 1"); 779 // Read register TCM_REG_CFC_INIT_CRD val and check if condition on val exist 780 IDLE_CHK_1(0x1F, TCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: CFC_INIT_CRD is not 1"); 781 // Read register CCM_REG_CFC_INIT_CRD val and check if condition on val exist 782 IDLE_CHK_1(0x1F, CCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CFC_INIT_CRD is not 1"); 783 // Read register XCM_REG_XQM_INIT_CRD val and check if condition on val exist 784 IDLE_CHK_1(0x1F, XCM_REG_XQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: XQM_INIT_CRD is not 32"); 785 // Read register UCM_REG_UQM_INIT_CRD val and check if condition on val exist 786 IDLE_CHK_1(0x1F, UCM_REG_UQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: UQM_INIT_CRD is not 32"); 787 // Read register TCM_REG_TQM_INIT_CRD val and check if condition on val exist 788 IDLE_CHK_1(0x1F, TCM_REG_TQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: TQM_INIT_CRD is not 32"); 789 // Read register CCM_REG_CQM_INIT_CRD val and check if condition on val exist 790 IDLE_CHK_1(0x1F, CCM_REG_CQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CQM_INIT_CRD is not 32"); 791 // Read register XCM_REG_TM_INIT_CRD val and check if condition on val exist 792 IDLE_CHK_1(0x1F, XCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: TM_INIT_CRD is not 4"); 793 // Read register UCM_REG_TM_INIT_CRD val and check if condition on val exist 794 IDLE_CHK_1(0x1F, UCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: TM_INIT_CRD is not 4"); 795 // Read register XCM_REG_FIC0_INIT_CRD val and check if condition on val exist 796 IDLE_CHK_1(0x1F, XCM_REG_FIC0_INIT_CRD, (val != 64), IDLE_CHK_WARNING, "XCM: FIC0_INIT_CRD is not 64"); 797 // Read register UCM_REG_FIC0_INIT_CRD val and check if condition on val exist 798 IDLE_CHK_1(0x1F, UCM_REG_FIC0_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: FIC0_INIT_CRD is not 64"); 799 // Read register TCM_REG_FIC0_INIT_CRD val and check if condition on val exist 800 IDLE_CHK_1(0x1F, TCM_REG_FIC0_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: FIC0_INIT_CRD is not 64"); 801 // Read register CCM_REG_FIC0_INIT_CRD val and check if condition on val exist 802 IDLE_CHK_1(0x1F, CCM_REG_FIC0_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: FIC0_INIT_CRD is not 64"); 803 // Read register XCM_REG_FIC1_INIT_CRD val and check if condition on val exist 804 IDLE_CHK_1(0x1F, XCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: FIC1_INIT_CRD is not 64"); 805 // Read register UCM_REG_FIC1_INIT_CRD val and check if condition on val exist 806 IDLE_CHK_1(0x1F, UCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: FIC1_INIT_CRD is not 64"); 807 // Read register TCM_REG_FIC1_INIT_CRD val and check if condition on val exist 808 IDLE_CHK_1(0x1F, TCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: FIC1_INIT_CRD is not 64"); 809 // Read register CCM_REG_FIC1_INIT_CRD val and check if condition on val exist 810 IDLE_CHK_1(0x1F, CCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: FIC1_INIT_CRD is not 64"); 811 // Read register XCM_REG_XX_FREE val and check if condition on val exist 812 IDLE_CHK_1(0x1, XCM_REG_XX_FREE, (val != 31), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: XX_FREE differs from expected 31"); 813 // Read register XCM_REG_XX_FREE val and check if condition on val exist 814 IDLE_CHK_1(0x1E, XCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: XX_FREE differs from expected 32"); 815 // Read register UCM_REG_XX_FREE val and check if condition on val exist 816 IDLE_CHK_1(0x1F, UCM_REG_XX_FREE, (val != 27), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: XX_FREE differs from expected 27"); 817 // Read register TCM_REG_XX_FREE val and check if condition on val exist 818 IDLE_CHK_1(0x7, TCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: XX_FREE differs from expected 32"); 819 // Read register TCM_REG_XX_FREE val and check if condition on val exist 820 IDLE_CHK_1(0x18, TCM_REG_XX_FREE, (val != 29), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: XX_FREE differs from expected 29"); 821 // Read register CCM_REG_XX_FREE val and check if condition on val exist 822 IDLE_CHK_1(0x1F, CCM_REG_XX_FREE, (val != 24), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: XX_FREE differs from expected 24"); 823 // Read register XSEM_REG_FAST_MEMORY + 0x18000 val and check if condition on val exist 824 IDLE_CHK_1(0x1F, XSEM_REG_FAST_MEMORY + 0x18000, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: FOC0 credit less than initial credit"); 825 // Read register XSEM_REG_FAST_MEMORY + 0x18040 val and check if condition on val exist 826 IDLE_CHK_1(0x1F, XSEM_REG_FAST_MEMORY + 0x18040, (val != 24), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: FOC1 credit less than initial credit"); 827 // Read register XSEM_REG_FAST_MEMORY + 0x18080 val and check if condition on val exist 828 IDLE_CHK_1(0x1F, XSEM_REG_FAST_MEMORY + 0x18080, (val != 12), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: FOC2 credit less than initial credit"); 829 // Read register USEM_REG_FAST_MEMORY + 0x18000 val and check if condition on val exist 830 IDLE_CHK_1(0x1F, USEM_REG_FAST_MEMORY + 0x18000, (val != 26), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: FOC0 credit less than initial credit"); 831 // Read register USEM_REG_FAST_MEMORY + 0x18040 val and check if condition on val exist 832 IDLE_CHK_1(0x1F, USEM_REG_FAST_MEMORY + 0x18040, (val != 78), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: FOC1 credit less than initial credit"); 833 // Read register USEM_REG_FAST_MEMORY + 0x18080 val and check if condition on val exist 834 IDLE_CHK_1(0x1F, USEM_REG_FAST_MEMORY + 0x18080, (val != 16), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: FOC2 credit less than initial credit"); 835 // Read register USEM_REG_FAST_MEMORY + 0x180C0 val and check if condition on val exist 836 IDLE_CHK_1(0x1F, USEM_REG_FAST_MEMORY + 0x180C0, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: FOC3 credit less than initial credit"); 837 // Read register TSEM_REG_FAST_MEMORY + 0x18000 val and check if condition on val exist 838 IDLE_CHK_1(0x1F, TSEM_REG_FAST_MEMORY + 0x18000, (val != 52), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: FOC0 credit less than initial credit"); 839 // Read register TSEM_REG_FAST_MEMORY + 0x18040 val and check if condition on val exist 840 IDLE_CHK_1(0x1F, TSEM_REG_FAST_MEMORY + 0x18040, (val != 24), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: FOC1 credit less than initial credit"); 841 // Read register TSEM_REG_FAST_MEMORY + 0x18080 val and check if condition on val exist 842 IDLE_CHK_1(0x1F, TSEM_REG_FAST_MEMORY + 0x18080, (val != 12), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: FOC2 credit less than initial credit"); 843 // Read register TSEM_REG_FAST_MEMORY + 0x180C0 val and check if condition on val exist 844 IDLE_CHK_1(0x1F, TSEM_REG_FAST_MEMORY + 0x180C0, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: FOC3 credit less than initial credit"); 845 // Read register CSEM_REG_FAST_MEMORY + 0x18000 val and check if condition on val exist 846 IDLE_CHK_1(0x1F, CSEM_REG_FAST_MEMORY + 0x18000, (val != 16), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: FOC0 credit less than initial credit"); 847 // Read register CSEM_REG_FAST_MEMORY + 0x18040 val and check if condition on val exist 848 IDLE_CHK_1(0x1F, CSEM_REG_FAST_MEMORY + 0x18040, (val != 18), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: FOC1 credit less than initial credit"); 849 // Read register CSEM_REG_FAST_MEMORY + 0x18080 val and check if condition on val exist 850 IDLE_CHK_1(0x1F, CSEM_REG_FAST_MEMORY + 0x18080, (val != 48), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: FOC2 credit less than initial credit"); 851 // Read register CSEM_REG_FAST_MEMORY + 0x180C0 val and check if condition on val exist 852 IDLE_CHK_1(0x1F, CSEM_REG_FAST_MEMORY + 0x180C0, (val != 14), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: FOC3 credit less than initial credit"); 853 // Read register PRS_REG_TSDM_CURRENT_CREDIT val and check if condition on val exist 854 IDLE_CHK_1(0x1F, PRS_REG_TSDM_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: TSDM current credit is not 0"); 855 // Read register PRS_REG_TCM_CURRENT_CREDIT val and check if condition on val exist 856 IDLE_CHK_1(0x1F, PRS_REG_TCM_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: TCM current credit is not 0"); 857 // Read register PRS_REG_CFC_LD_CURRENT_CREDIT val and check if condition on val exist 858 IDLE_CHK_1(0x1F, PRS_REG_CFC_LD_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: CFC_LD current credit is not 0"); 859 // Read register PRS_REG_CFC_SEARCH_CURRENT_CREDIT val and check if condition on val exist 860 IDLE_CHK_1(0x1F, PRS_REG_CFC_SEARCH_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: CFC_SEARCH current credit is not 0"); 861 // Read register PRS_REG_SRC_CURRENT_CREDIT val and check if condition on val exist 862 IDLE_CHK_1(0x1F, PRS_REG_SRC_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: SRCH current credit is not 0"); 863 // Read register PRS_REG_PENDING_BRB_PRS_RQ val and check if condition on val exist 864 IDLE_CHK_1(0x1F, PRS_REG_PENDING_BRB_PRS_RQ, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: PENDING_BRB_PRS_RQ is not 0"); 865 // Read register PRS_REG_PENDING_BRB_CAC0_RQ val in loop (incr by 4) and check if condition on val exist 866 IDLE_CHK_2(0x1F, PRS_REG_PENDING_BRB_CAC0_RQ, 5, 4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: PENDING_BRB_CAC_RQ is not 0"); 867 // Read register PRS_REG_SERIAL_NUM_STATUS_LSB val and check if condition on val exist 868 IDLE_CHK_1(0x1F, PRS_REG_SERIAL_NUM_STATUS_LSB, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: SERIAL_NUM_STATUS_LSB is not 0"); 869 // Read register PRS_REG_SERIAL_NUM_STATUS_MSB val and check if condition on val exist 870 IDLE_CHK_1(0x1F, PRS_REG_SERIAL_NUM_STATUS_MSB, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: SERIAL_NUM_STATUS_MSB is not 0"); 871 // Read register CDU_REG_ERROR_DATA val and check if condition on val exist 872 IDLE_CHK_1(0x1F, CDU_REG_ERROR_DATA, (val != 0), IDLE_CHK_ERROR, "CDU: ERROR_DATA is not 0"); 873 // Read register CCM_REG_STORM_LENGTH_MIS val and check if condition on val exist 874 IDLE_CHK_1(0x1F, CCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: STORM declared message length unequal to actual"); 875 // Read register CCM_REG_CSDM_LENGTH_MIS val and check if condition on val exist 876 IDLE_CHK_1(0x1F, CCM_REG_CSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: CSDM declared message length unequal to actual"); 877 // Read register CCM_REG_TSEM_LENGTH_MIS val and check if condition on val exist 878 IDLE_CHK_1(0x1F, CCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: TSEM declared message length unequal to actual"); 879 // Read register CCM_REG_XSEM_LENGTH_MIS val and check if condition on val exist 880 IDLE_CHK_1(0x1F, CCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: XSEM declared message length unequal to actual"); 881 // Read register CCM_REG_USEM_LENGTH_MIS val and check if condition on val exist 882 IDLE_CHK_1(0x1F, CCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: USEM declared message length unequal to actual"); 883 // Read register CCM_REG_PBF_LENGTH_MIS val and check if condition on val exist 884 IDLE_CHK_1(0x1F, CCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "CCM: PBF declared message length unequal to actual"); 885 // Read register TCM_REG_STORM_LENGTH_MIS val and check if condition on val exist 886 IDLE_CHK_1(0x1F, TCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: STORM declared message length unequal to actual"); 887 // Read register TCM_REG_TSDM_LENGTH_MIS val and check if condition on val exist 888 IDLE_CHK_1(0x1F, TCM_REG_TSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: TSDM declared message length unequal to actual"); 889 // Read register TCM_REG_PRS_LENGTH_MIS val and check if condition on val exist 890 IDLE_CHK_1(0x1F, TCM_REG_PRS_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: PRS declared message length unequal to actual"); 891 // Read register TCM_REG_PBF_LENGTH_MIS val and check if condition on val exist 892 IDLE_CHK_1(0x1F, TCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: PBF declared message length unequal to actual"); 893 // Read register TCM_REG_USEM_LENGTH_MIS val and check if condition on val exist 894 IDLE_CHK_1(0x1F, TCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: USEM declared message length unequal to actual"); 895 // Read register TCM_REG_CSEM_LENGTH_MIS val and check if condition on val exist 896 IDLE_CHK_1(0x1F, TCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "TCM: CSEM declared message length unequal to actual"); 897 // Read register UCM_REG_STORM_LENGTH_MIS val and check if condition on val exist 898 IDLE_CHK_1(0x1F, UCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: STORM declared message length unequal to actual"); 899 // Read register UCM_REG_USDM_LENGTH_MIS val and check if condition on val exist 900 IDLE_CHK_1(0x1F, UCM_REG_USDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: USDM declared message length unequal to actual"); 901 // Read register UCM_REG_TSEM_LENGTH_MIS val and check if condition on val exist 902 IDLE_CHK_1(0x1F, UCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: TSEM declared message length unequal to actual"); 903 // Read register UCM_REG_CSEM_LENGTH_MIS val and check if condition on val exist 904 IDLE_CHK_1(0x1F, UCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: CSEM declared message length unequal to actual"); 905 // Read register UCM_REG_XSEM_LENGTH_MIS val and check if condition on val exist 906 IDLE_CHK_1(0x1F, UCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: XSEM declared message length unequal to actual"); 907 // Read register UCM_REG_DORQ_LENGTH_MIS val and check if condition on val exist 908 IDLE_CHK_1(0x1F, UCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "UCM: DORQ declared message length unequal to actual"); 909 // Read register XCM_REG_STORM_LENGTH_MIS val and check if condition on val exist 910 IDLE_CHK_1(0x1F, XCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: STORM declared message length unequal to actual"); 911 // Read register XCM_REG_XSDM_LENGTH_MIS val and check if condition on val exist 912 IDLE_CHK_1(0x1F, XCM_REG_XSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: XSDM declared message length unequal to actual"); 913 // Read register XCM_REG_TSEM_LENGTH_MIS val and check if condition on val exist 914 IDLE_CHK_1(0x1F, XCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: TSEM declared message length unequal to actual"); 915 // Read register XCM_REG_CSEM_LENGTH_MIS val and check if condition on val exist 916 IDLE_CHK_1(0x1F, XCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: CSEM declared message length unequal to actual"); 917 // Read register XCM_REG_USEM_LENGTH_MIS val and check if condition on val exist 918 IDLE_CHK_1(0x1F, XCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: USEM declared message length unequal to actual"); 919 // Read register XCM_REG_DORQ_LENGTH_MIS val and check if condition on val exist 920 IDLE_CHK_1(0x1F, XCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: DORQ declared message length unequal to actual"); 921 // Read register XCM_REG_PBF_LENGTH_MIS val and check if condition on val exist 922 IDLE_CHK_1(0x1F, XCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: PBF declared message length unequal to actual"); 923 // Read register XCM_REG_NIG0_LENGTH_MIS val and check if condition on val exist 924 IDLE_CHK_1(0x1F, XCM_REG_NIG0_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: NIG0 declared message length unequal to actual"); 925 // Read register XCM_REG_NIG1_LENGTH_MIS val and check if condition on val exist 926 IDLE_CHK_1(0x1F, XCM_REG_NIG1_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR, "XCM: NIG1 declared message length unequal to actual"); 927 // Read register QM_REG_XQM_WRC_FIFOLVL val and check if condition on val exist 928 IDLE_CHK_1(0x1F, QM_REG_XQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: XQM wrc_fifolvl is not 0"); 929 // Read register QM_REG_UQM_WRC_FIFOLVL val and check if condition on val exist 930 IDLE_CHK_1(0x1F, QM_REG_UQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: UQM wrc_fifolvl is not 0"); 931 // Read register QM_REG_TQM_WRC_FIFOLVL val and check if condition on val exist 932 IDLE_CHK_1(0x1F, QM_REG_TQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: TQM wrc_fifolvl is not 0"); 933 // Read register QM_REG_CQM_WRC_FIFOLVL val and check if condition on val exist 934 IDLE_CHK_1(0x1F, QM_REG_CQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: CQM wrc_fifolvl is not 0"); 935 // Read register QM_REG_QSTATUS_LOW val and check if condition on val exist 936 IDLE_CHK_1(0x1F, QM_REG_QSTATUS_LOW, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: QSTATUS_LOW is not 0"); 937 // Read register QM_REG_QSTATUS_HIGH val and check if condition on val exist 938 IDLE_CHK_1(0x1F, QM_REG_QSTATUS_HIGH, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: QSTATUS_HIGH is not 0"); 939 // Read register QM_REG_PAUSESTATE0 val and check if condition on val exist 940 IDLE_CHK_1(0x1F, QM_REG_PAUSESTATE0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: PAUSESTATE0 is not 0"); 941 // Read register QM_REG_PAUSESTATE1 val and check if condition on val exist 942 IDLE_CHK_1(0x1F, QM_REG_PAUSESTATE1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: PAUSESTATE1 is not 0"); 943 // Read register QM_REG_OVFQNUM val and check if condition on val exist 944 IDLE_CHK_1(0x1F, QM_REG_OVFQNUM, (val != 0), IDLE_CHK_ERROR, "QM: OVFQNUM is not 0"); 945 // Read register QM_REG_OVFERROR val and check if condition on val exist 946 IDLE_CHK_1(0x1F, QM_REG_OVFERROR, (val != 0), IDLE_CHK_ERROR, "QM: OVFERROR is not 0"); 947 // Special check for QM PTRTBL 948 IDLE_CHK_6(0x1F, QM_REG_PTRTBL, 64, 8, IDLE_CHK_ERROR_NO_TRAFFIC); 949 // Read register BRB1_REG_BRB1_PRTY_STS val and check if condition on val exist 950 IDLE_CHK_1(0x1F, BRB1_REG_BRB1_PRTY_STS, ((val & ~ 0x8) != 0), IDLE_CHK_WARNING, "BRB1: parity status is not 0"); 951 // Read register CDU_REG_CDU_PRTY_STS val and check if condition on val exist 952 IDLE_CHK_1(0x1F, CDU_REG_CDU_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "CDU: parity status is not 0"); 953 // Read register CFC_REG_CFC_PRTY_STS val and check if condition on val exist 954 IDLE_CHK_1(0x1F, CFC_REG_CFC_PRTY_STS, ((val & ~0x2)!= 0), IDLE_CHK_WARNING, "CFC: parity status is not 0"); 955 // Read register CSDM_REG_CSDM_PRTY_STS val and check if condition on val exist 956 IDLE_CHK_1(0x1F, CSDM_REG_CSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "CSDM: parity status is not 0"); 957 // Read register DBG_REG_DBG_PRTY_STS val and check if condition on val exist 958 IDLE_CHK_1(0x3, DBG_REG_DBG_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "DBG: parity status is not 0"); 959 // Read register DMAE_REG_DMAE_PRTY_STS val and check if condition on val exist 960 IDLE_CHK_1(0x1F, DMAE_REG_DMAE_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "DMAE: parity status is not 0"); 961 // Read register DORQ_REG_DORQ_PRTY_STS val and check if condition on val exist 962 IDLE_CHK_1(0x1F, DORQ_REG_DORQ_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "DORQ: parity status is not 0"); 963 // Read register TCM_REG_TCM_PRTY_STS val and check if condition on val exist 964 IDLE_CHK_1(0x1, TCM_REG_TCM_PRTY_STS, ((val & ~0x3ffc0) != 0), IDLE_CHK_WARNING, "TCM: parity status is not 0"); 965 // Read register TCM_REG_TCM_PRTY_STS val and check if condition on val exist 966 IDLE_CHK_1(0x1E, TCM_REG_TCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "TCM: parity status is not 0"); 967 // Read register CCM_REG_CCM_PRTY_STS val and check if condition on val exist 968 IDLE_CHK_1(0x1, CCM_REG_CCM_PRTY_STS, ((val & ~0x3ffc0) != 0), IDLE_CHK_WARNING, "CCM: parity status is not 0"); 969 // Read register CCM_REG_CCM_PRTY_STS val and check if condition on val exist 970 IDLE_CHK_1(0x1E, CCM_REG_CCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "CCM: parity status is not 0"); 971 // Read register UCM_REG_UCM_PRTY_STS val and check if condition on val exist 972 IDLE_CHK_1(0x1, UCM_REG_UCM_PRTY_STS, ((val & ~0x3ffc0) != 0), IDLE_CHK_WARNING, "UCM: parity status is not 0"); 973 // Read register UCM_REG_UCM_PRTY_STS val and check if condition on val exist 974 IDLE_CHK_1(0x1E, UCM_REG_UCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "UCM: parity status is not 0"); 975 // Read register XCM_REG_XCM_PRTY_STS val and check if condition on val exist 976 IDLE_CHK_1(0x1, XCM_REG_XCM_PRTY_STS, ((val & ~0x3ffc0) != 0), IDLE_CHK_WARNING, "XCM: parity status is not 0"); 977 // Read register XCM_REG_XCM_PRTY_STS val and check if condition on val exist 978 IDLE_CHK_1(0x1E, XCM_REG_XCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "XCM: parity status is not 0"); 979 // Read register HC_REG_HC_PRTY_STS val and check if condition on val exist 980 IDLE_CHK_1(0x1, HC_REG_HC_PRTY_STS, ((val& ~0x1) != 0), IDLE_CHK_WARNING, "HC: parity status is not 0"); 981 // Read register MISC_REG_MISC_PRTY_STS val and check if condition on val exist 982 IDLE_CHK_1(0x1, MISC_REG_MISC_PRTY_STS, ((val& ~0x1) != 0), IDLE_CHK_WARNING, "MISC: parity status is not 0"); 983 // Read register PRS_REG_PRS_PRTY_STS val and check if condition on val exist 984 IDLE_CHK_1(0x1F, PRS_REG_PRS_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "PRS: parity status is not 0"); 985 // Read register PXP_REG_PXP_PRTY_STS val and check if condition on val exist 986 IDLE_CHK_1(0x1F, PXP_REG_PXP_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "PXP: parity status is not 0"); 987 // Read register QM_REG_QM_PRTY_STS val and check if condition on val exist 988 IDLE_CHK_1(0x1F, QM_REG_QM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "QM: parity status is not 0"); 989 // Read register SRC_REG_SRC_PRTY_STS val and check if condition on val exist 990 IDLE_CHK_1(0x1, SRC_REG_SRC_PRTY_STS, ((val & ~0x4) != 0), IDLE_CHK_WARNING, "SRCH: parity status is not 0"); 991 // Read register TSDM_REG_TSDM_PRTY_STS val and check if condition on val exist 992 IDLE_CHK_1(0x1F, TSDM_REG_TSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "TSDM: parity status is not 0"); 993 // Read register USDM_REG_USDM_PRTY_STS val and check if condition on val exist 994 IDLE_CHK_1(0x1F, USDM_REG_USDM_PRTY_STS, ((val & ~0x20) != 0), IDLE_CHK_WARNING, "USDM: parity status is not 0"); 995 // Read register XSDM_REG_XSDM_PRTY_STS val and check if condition on val exist 996 IDLE_CHK_1(0x1F, XSDM_REG_XSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "XSDM: parity status is not 0"); 997 // Read register GRCBASE_XPB + PB_REG_PB_PRTY_STS val and check if condition on val exist 998 IDLE_CHK_1(0x1F, GRCBASE_XPB + PB_REG_PB_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "XPB: parity status is not 0"); 999 // Read register GRCBASE_UPB + PB_REG_PB_PRTY_STS val and check if condition on val exist 1000 IDLE_CHK_1(0x1F, GRCBASE_UPB + PB_REG_PB_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "UPB: parity status is not 0"); 1001 // Read register CSEM_REG_CSEM_PRTY_STS_0 val and check if condition on val exist 1002 IDLE_CHK_1(0x1F, CSEM_REG_CSEM_PRTY_STS_0, (val != 0), IDLE_CHK_WARNING, "CSEM: parity status 0 is not 0"); 1003 // Read register PXP2_REG_PXP2_PRTY_STS_0 val and check if condition on val exist 1004 IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0xfff40020) != 0) , IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0"); 1005 // Read register PXP2_REG_PXP2_PRTY_STS_0 val and check if condition on val exist 1006 IDLE_CHK_1(0x1E, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0x20) != 0), IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0"); 1007 // Read register TSEM_REG_TSEM_PRTY_STS_0 val and check if condition on val exist 1008 IDLE_CHK_1(0x1F, TSEM_REG_TSEM_PRTY_STS_0, (val != 0), IDLE_CHK_WARNING, "TSEM: parity status 0 is not 0"); 1009 // Read register USEM_REG_USEM_PRTY_STS_0 val and check if condition on val exist 1010 IDLE_CHK_1(0x1F, USEM_REG_USEM_PRTY_STS_0, (val != 0), IDLE_CHK_WARNING, "USEM: parity status 0 is not 0"); 1011 // Read register XSEM_REG_XSEM_PRTY_STS_0 val and check if condition on val exist 1012 IDLE_CHK_1(0x1F, XSEM_REG_XSEM_PRTY_STS_0, (val != 0), IDLE_CHK_WARNING, "XSEM: parity status 0 is not 0"); 1013 // Read register CSEM_REG_CSEM_PRTY_STS_1 val and check if condition on val exist 1014 IDLE_CHK_1(0x1F, CSEM_REG_CSEM_PRTY_STS_1, (val != 0), IDLE_CHK_WARNING, "CSEM: parity status 1 is not 0"); 1015 // Read register PXP2_REG_PXP2_PRTY_STS_1 val and check if condition on val exist 1016 IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_1, ((val & ~0x20) != 0), IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0"); 1017 // Read register PXP2_REG_PXP2_PRTY_STS_1 val and check if condition on val exist 1018 IDLE_CHK_1(0x1E, PXP2_REG_PXP2_PRTY_STS_1, (val != 0), IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0"); 1019 // Read register TSEM_REG_TSEM_PRTY_STS_1 val and check if condition on val exist 1020 IDLE_CHK_1(0x1F, TSEM_REG_TSEM_PRTY_STS_1, (val != 0), IDLE_CHK_WARNING, "TSEM: parity status 1 is not 0"); 1021 // Read register USEM_REG_USEM_PRTY_STS_1 val and check if condition on val exist 1022 IDLE_CHK_1(0x1F, USEM_REG_USEM_PRTY_STS_1, (val != 0), IDLE_CHK_WARNING, "USEM: parity status 1 is not 0"); 1023 // Read register XSEM_REG_XSEM_PRTY_STS_1 val and check if condition on val exist 1024 IDLE_CHK_1(0x1F, XSEM_REG_XSEM_PRTY_STS_1, (val != 0), IDLE_CHK_WARNING, "XSEM: parity status 1 is not 0"); 1025 // Read register PGLUE_B_REG_PGLUE_B_PRTY_STS val and check if condition on val exist 1026 IDLE_CHK_1(0x1C, PGLUE_B_REG_PGLUE_B_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "PGLUE_B: parity status is not 0"); 1027 // Read register QM_REG_QTASKCTR_EXT_A_0 val in loop (incr by 4) and check if condition on val exist 1028 IDLE_CHK_2(0x2, QM_REG_QTASKCTR_EXT_A_0, 64, 4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Q_EXT_A (upper 64 queues), Queue is not empty"); 1029 // Read register QM_REG_QSTATUS_LOW_EXT_A val and check if condition on val exist 1030 IDLE_CHK_1(0x2, QM_REG_QSTATUS_LOW_EXT_A, (val != 0), IDLE_CHK_ERROR, "QM: QSTATUS_LOW_EXT_A is not 0"); 1031 // Read register QM_REG_QSTATUS_HIGH_EXT_A val and check if condition on val exist 1032 IDLE_CHK_1(0x2, QM_REG_QSTATUS_HIGH_EXT_A, (val != 0), IDLE_CHK_ERROR, "QM: QSTATUS_HIGH_EXT_A is not 0"); 1033 // Read register QM_REG_PAUSESTATE2 val and check if condition on val exist 1034 IDLE_CHK_1(0x1E, QM_REG_PAUSESTATE2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: PAUSESTATE2 is not 0"); 1035 // Read register QM_REG_PAUSESTATE3 val and check if condition on val exist 1036 IDLE_CHK_1(0x1E, QM_REG_PAUSESTATE3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: PAUSESTATE3 is not 0"); 1037 // Read register QM_REG_PAUSESTATE4 val and check if condition on val exist 1038 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE4, (val != 0), IDLE_CHK_ERROR, "QM: PAUSESTATE4 is not 0"); 1039 // Read register QM_REG_PAUSESTATE5 val and check if condition on val exist 1040 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE5, (val != 0), IDLE_CHK_ERROR, "QM: PAUSESTATE5 is not 0"); 1041 // Read register QM_REG_PAUSESTATE6 val and check if condition on val exist 1042 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE6, (val != 0), IDLE_CHK_ERROR, "QM: PAUSESTATE6 is not 0"); 1043 // Read register QM_REG_PAUSESTATE7 val and check if condition on val exist 1044 IDLE_CHK_1(0x2, QM_REG_PAUSESTATE7, (val != 0), IDLE_CHK_ERROR, "QM: PAUSESTATE7 is not 0"); 1045 // Special check for QM PTRTBL 1046 IDLE_CHK_6(0x2, QM_REG_PTRTBL_EXT_A, 64, 8, IDLE_CHK_ERROR_NO_TRAFFIC); 1047 // Read register MISC_REG_AEU_SYS_KILL_OCCURRED val and check if condition on val exist 1048 IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_OCCURRED, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd;"); 1049 // Read register MISC_REG_AEU_SYS_KILL_STATUS_0 val and check if condition on val exist 1050 IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_STATUS_0, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd; status_0 register"); 1051 // Read register MISC_REG_AEU_SYS_KILL_STATUS_1 val and check if condition on val exist 1052 IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_STATUS_1, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd; status_1 register"); 1053 // Read register MISC_REG_AEU_SYS_KILL_STATUS_2 val and check if condition on val exist 1054 IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_STATUS_2, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd; status_2 register"); 1055 // Read register MISC_REG_AEU_SYS_KILL_STATUS_3 val and check if condition on val exist 1056 IDLE_CHK_1(0x1E, MISC_REG_AEU_SYS_KILL_STATUS_3, (val != 0), IDLE_CHK_ERROR, "MISC: system kill occurd; status_3 register"); 1057 // Read register MISC_REG_PCIE_HOT_RESET val and check if condition on val exist 1058 IDLE_CHK_1(0x1E, MISC_REG_PCIE_HOT_RESET, (val != 0), IDLE_CHK_WARNING, "MISC: pcie_rst_b was asserted without perst assertion"); 1059 // Read register NIG_REG_NIG_INT_STS_0 val and check if condition on val exist 1060 IDLE_CHK_1(0x1F, NIG_REG_NIG_INT_STS_0, ((val & ~0x300) != 0), IDLE_CHK_ERROR, "NIG: interrupt 0 is active"); 1061 // Read register NIG_REG_NIG_INT_STS_0 val and check if condition on val exist 1062 IDLE_CHK_1(0x1F, NIG_REG_NIG_INT_STS_0, (val == 0x300), IDLE_CHK_WARNING, "NIG: Access to BMAC while not active. If tested on FPGA, ignore this warning."); 1063 // Read register NIG_REG_NIG_INT_STS_1 val and check if condition on val exist 1064 IDLE_CHK_1(0x1F, NIG_REG_NIG_INT_STS_1, ((val & 0x783FF0F) != 0), IDLE_CHK_ERROR, "NIG: interrupt 1 is active"); 1065 // Read register NIG_REG_NIG_INT_STS_1 val and check if condition on val exist 1066 IDLE_CHK_1(0x1F, NIG_REG_NIG_INT_STS_1, ((val & ~0x783FF0F) != 0), IDLE_CHK_WARNING, "NIG: port cos was paused too long"); 1067 // Read register NIG_REG_NIG_PRTY_STS val and check if condition on val exist 1068 IDLE_CHK_1(0x2, NIG_REG_NIG_PRTY_STS, ((val & ~0xFFC00000) != 0), IDLE_CHK_ERROR, "NIG: parity interrupt is active"); 1069 // Read register NIG_REG_NIG_PRTY_STS_0 val and check if condition on val exist 1070 IDLE_CHK_1(0x1C, NIG_REG_NIG_PRTY_STS_0, ((val & ~0xFFC00000) != 0), IDLE_CHK_ERROR, "NIG: parity 0 interrupt is active"); 1071 // Read register NIG_REG_NIG_PRTY_STS_1 val and check if condition on val exist 1072 IDLE_CHK_1(0x4, NIG_REG_NIG_PRTY_STS_1, ((val & 0xff) != 0), IDLE_CHK_ERROR, "NIG: parity 1 interrupt is active"); 1073 // Read register NIG_REG_NIG_PRTY_STS_1 val and check if condition on val exist 1074 IDLE_CHK_1(0x18, NIG_REG_NIG_PRTY_STS_1, (val != 0), IDLE_CHK_ERROR, "NIG: parity 1 interrupt is active"); 1075 // Read register TSEM_REG_TSEM_INT_STS_0 val and check if condition on val exist 1076 IDLE_CHK_1(0x1F, TSEM_REG_TSEM_INT_STS_0, ((val & ~0x10000000) != 0), IDLE_CHK_WARNING, "TSEM: interrupt 0 is active"); 1077 // Read register TSEM_REG_TSEM_INT_STS_0 val and check if condition on val exist 1078 IDLE_CHK_1(0x1F, TSEM_REG_TSEM_INT_STS_0, (val == 0x10000000), IDLE_CHK_WARNING, "TSEM: interrupt 0 is active"); 1079 // Read register TSEM_REG_TSEM_INT_STS_1 val and check if condition on val exist 1080 IDLE_CHK_1(0x1F, TSEM_REG_TSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "TSEM: interrupt 1 is active"); 1081 // Read register CSEM_REG_CSEM_INT_STS_0 val and check if condition on val exist 1082 IDLE_CHK_1(0x1F, CSEM_REG_CSEM_INT_STS_0, ((val & ~0x10000000) != 0), IDLE_CHK_WARNING, "CSEM: interrupt 0 is active"); 1083 // Read register CSEM_REG_CSEM_INT_STS_0 val and check if condition on val exist 1084 IDLE_CHK_1(0x1F, CSEM_REG_CSEM_INT_STS_0, (val == 0x10000000), IDLE_CHK_WARNING, "CSEM: interrupt 0 is active"); 1085 // Read register CSEM_REG_CSEM_INT_STS_1 val and check if condition on val exist 1086 IDLE_CHK_1(0x1F, CSEM_REG_CSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "CSEM: interrupt 1 is active"); 1087 // Read register USEM_REG_USEM_INT_STS_0 val and check if condition on val exist 1088 IDLE_CHK_1(0x1F, USEM_REG_USEM_INT_STS_0, ((val & ~0x10000000) != 0), IDLE_CHK_WARNING, "USEM: interrupt 0 is active"); 1089 // Read register USEM_REG_USEM_INT_STS_0 val and check if condition on val exist 1090 IDLE_CHK_1(0x1F, USEM_REG_USEM_INT_STS_0, (val == 0x10000000), IDLE_CHK_WARNING, "USEM: interrupt 0 is active"); 1091 // Read register USEM_REG_USEM_INT_STS_1 val and check if condition on val exist 1092 IDLE_CHK_1(0x1F, USEM_REG_USEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "USEM: interrupt 1 is active"); 1093 // Read register XSEM_REG_XSEM_INT_STS_0 val and check if condition on val exist 1094 IDLE_CHK_1(0x1F, XSEM_REG_XSEM_INT_STS_0, ((val & ~0x10000000) != 0), IDLE_CHK_WARNING, "XSEM: interrupt 0 is active"); 1095 // Read register XSEM_REG_XSEM_INT_STS_0 val and check if condition on val exist 1096 IDLE_CHK_1(0x1F, XSEM_REG_XSEM_INT_STS_0, (val == 0x10000000), IDLE_CHK_WARNING, "XSEM: interrupt 0 is active"); 1097 // Read register XSEM_REG_XSEM_INT_STS_1 val and check if condition on val exist 1098 IDLE_CHK_1(0x1F, XSEM_REG_XSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "XSEM: interrupt 1 is active"); 1099 // Read register TSDM_REG_TSDM_INT_STS_0 val and check if condition on val exist 1100 IDLE_CHK_1(0x1F, TSDM_REG_TSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, "TSDM: interrupt 0 is active"); 1101 // Read register TSDM_REG_TSDM_INT_STS_1 val and check if condition on val exist 1102 IDLE_CHK_1(0x1F, TSDM_REG_TSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "TSDM: interrupt 0 is active"); 1103 // Read register CSDM_REG_CSDM_INT_STS_0 val and check if condition on val exist 1104 IDLE_CHK_1(0x1F, CSDM_REG_CSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, "CSDM: interrupt 0 is active"); 1105 // Read register CSDM_REG_CSDM_INT_STS_1 val and check if condition on val exist 1106 IDLE_CHK_1(0x1F, CSDM_REG_CSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "CSDM: interrupt 0 is active"); 1107 // Read register USDM_REG_USDM_INT_STS_0 val and check if condition on val exist 1108 IDLE_CHK_1(0x1F, USDM_REG_USDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, "USDM: interrupt 0 is active"); 1109 // Read register USDM_REG_USDM_INT_STS_1 val and check if condition on val exist 1110 IDLE_CHK_1(0x1F, USDM_REG_USDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "USDM: interrupt 0 is active"); 1111 // Read register XSDM_REG_XSDM_INT_STS_0 val and check if condition on val exist 1112 IDLE_CHK_1(0x1F, XSDM_REG_XSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR, "XSDM: interrupt 0 is active"); 1113 // Read register XSDM_REG_XSDM_INT_STS_1 val and check if condition on val exist 1114 IDLE_CHK_1(0x1F, XSDM_REG_XSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR, "XSDM: interrupt 0 is active"); 1115 // Read register HC_REG_HC_PRTY_STS val and check if condition on val exist 1116 IDLE_CHK_1(0x2, HC_REG_HC_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "HC: parity status is not 0"); 1117 // Read register MISC_REG_MISC_PRTY_STS val and check if condition on val exist 1118 IDLE_CHK_1(0x1E, MISC_REG_MISC_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "MISC: parity status is not 0"); 1119 // Read register SRC_REG_SRC_PRTY_STS val and check if condition on val exist 1120 IDLE_CHK_1(0x1E, SRC_REG_SRC_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "SRCH: parity status is not 0"); 1121 // Read register QM_REG_BYTECRD0 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1122 IDLE_CHK_3(0xC, QM_REG_BYTECRD0, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 0 is not equal to initial credit"); 1123 // Read register QM_REG_BYTECRD1 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1124 IDLE_CHK_3(0xC, QM_REG_BYTECRD1, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 1 is not equal to initial credit"); 1125 // Read register QM_REG_BYTECRD2 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1126 IDLE_CHK_3(0xC, QM_REG_BYTECRD2, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 2 is not equal to initial credit"); 1127 // Read register QM_REG_VOQCRDERRREG val and check if condition on val exist 1128 IDLE_CHK_1(0x1C, QM_REG_VOQCRDERRREG, ((val & 0xFFFF) != 0), IDLE_CHK_ERROR, "QM: VOQ credit error register is not 0 (VOQ credit overflow/underflow)"); 1129 // Read register QM_REG_BYTECRDERRREG val and check if condition on val exist 1130 IDLE_CHK_1(0x1C, QM_REG_BYTECRDERRREG, ((val & 0xFFF) != 0), IDLE_CHK_ERROR, "QM: Byte credit error register is not 0 (Byte credit overflow/underflow)"); 1131 // Read register PGLUE_B_REG_FLR_REQUEST_VF_31_0 val and check if condition on val exist 1132 IDLE_CHK_1(0x1C, PGLUE_B_REG_FLR_REQUEST_VF_31_0, (val != 0), IDLE_CHK_WARNING, "PGL: FLR request is set for VF addresses 31-0"); 1133 // Read register PGLUE_B_REG_FLR_REQUEST_VF_63_32 val and check if condition on val exist 1134 IDLE_CHK_1(0x1C, PGLUE_B_REG_FLR_REQUEST_VF_63_32, (val != 0), IDLE_CHK_WARNING, "PGL: FLR request is set for VF addresses 63-32"); 1135 // Read register PGLUE_B_REG_FLR_REQUEST_VF_95_64 val and check if condition on val exist 1136 IDLE_CHK_1(0x1C, PGLUE_B_REG_FLR_REQUEST_VF_95_64, (val != 0), IDLE_CHK_WARNING, "PGL: FLR request is set for VF addresses 95-64"); 1137 // Read register PGLUE_B_REG_FLR_REQUEST_VF_127_96 val and check if condition on val exist 1138 IDLE_CHK_1(0x1C, PGLUE_B_REG_FLR_REQUEST_VF_127_96, (val != 0), IDLE_CHK_WARNING, "PGL: FLR request is set for VF addresses 127-96"); 1139 // Read register PGLUE_B_REG_FLR_REQUEST_PF_7_0 val and check if condition on val exist 1140 IDLE_CHK_1(0x1C, PGLUE_B_REG_FLR_REQUEST_PF_7_0, (val != 0), IDLE_CHK_WARNING, "PGL: FLR request is set for PF addresses 7-0"); 1141 // Read register PGLUE_B_REG_SR_IOV_DISABLED_REQUEST val and check if condition on val exist 1142 IDLE_CHK_1(0x1C, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST, (val != 0), IDLE_CHK_WARNING, "PGL: SR-IOV disable request is set "); 1143 // Read register PGLUE_B_REG_CFG_SPACE_A_REQUEST val and check if condition on val exist 1144 IDLE_CHK_1(0x1C, PGLUE_B_REG_CFG_SPACE_A_REQUEST, (val != 0), IDLE_CHK_WARNING, "PGL: Cfg-Space A request is set"); 1145 // Read register PGLUE_B_REG_CFG_SPACE_B_REQUEST val and check if condition on val exist 1146 IDLE_CHK_1(0x1C, PGLUE_B_REG_CFG_SPACE_B_REQUEST, (val != 0), IDLE_CHK_WARNING, "PGL: Cfg-Space B request is set"); 1147 // Read register IGU_REG_ERROR_HANDLING_DATA_VALID val and check if condition on val exist 1148 IDLE_CHK_1(0x1C, IGU_REG_ERROR_HANDLING_DATA_VALID, (val != 0), IDLE_CHK_WARNING, "IGU: some unauthorized commands arrived to the IGU. Use igu_dump_fifo utility for more details."); 1149 // Read register IGU_REG_ATTN_WRITE_DONE_PENDING val and check if condition on val exist 1150 IDLE_CHK_1(0x1C, IGU_REG_ATTN_WRITE_DONE_PENDING, (val != 0), IDLE_CHK_WARNING, "IGU attention message write done pending is not empty"); 1151 // Read register IGU_REG_WRITE_DONE_PENDING val and check if condition on val exist 1152 IDLE_CHK_1(0x1C, IGU_REG_WRITE_DONE_PENDING, (val != 0), IDLE_CHK_WARNING, "IGU MSI/MSIX message write done pending is not empty"); 1153 // Read register IGU_REG_IGU_PRTY_STS val and check if condition on val exist 1154 IDLE_CHK_1(0x1C, IGU_REG_IGU_PRTY_STS, (val != 0), IDLE_CHK_WARNING, "IGU: parity status is not 0"); 1155 // Read register MISC_REG_GRC_TIMEOUT_ATTN val1 and register MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 val2 and check if condition on val1,val2 exist 1156 IDLE_CHK_3(0x1E, MISC_REG_GRC_TIMEOUT_ATTN, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (FUNC_0)."); 1157 // Read register MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID val1 and register MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 val2 and check if condition on val1,val2 exist 1158 IDLE_CHK_3(0x1C, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (FUNC_0)."); 1159 // Read register MISC_REG_GRC_TIMEOUT_ATTN val1 and register MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 val2 and check if condition on val1,val2 exist 1160 IDLE_CHK_3(0x1E, MISC_REG_GRC_TIMEOUT_ATTN, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (FUNC_1)."); 1161 // Read register MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID val1 and register MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 val2 and check if condition on val1,val2 exist 1162 IDLE_CHK_3(0x1C, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (FUNC_1)."); 1163 // Read register MISC_REG_GRC_TIMEOUT_ATTN val1 and register MISC_REG_AEU_AFTER_INVERT_4_MCP val2 and check if condition on val1,val2 exist 1164 IDLE_CHK_3(0x1E, MISC_REG_GRC_TIMEOUT_ATTN, MISC_REG_AEU_AFTER_INVERT_4_MCP, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (MCP)."); 1165 // Read register MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID val1 and register MISC_REG_AEU_AFTER_INVERT_4_MCP val2 and check if condition on val1,val2 exist 1166 IDLE_CHK_3(0x1C, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID, MISC_REG_AEU_AFTER_INVERT_4_MCP, ((val & 0x4000000) != 0), IDLE_CHK_ERROR, "MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (MCP)."); 1167 // Read register IGU_REG_SILENT_DROP val and check if condition on val exist 1168 IDLE_CHK_1(0x1C, IGU_REG_SILENT_DROP, (val != 0), IDLE_CHK_ERROR, "Some messages were not executed in the IGU."); 1169 // Read register PXP2_REG_PSWRQ_BW_CREDIT val and check if condition on val exist 1170 IDLE_CHK_1(0x1C, PXP2_REG_PSWRQ_BW_CREDIT, (val != 0x2D), IDLE_CHK_ERROR, "PXP2: rq_read_credit and rq_write_credit are not 5"); 1171 // Read register IGU_REG_SB_CTRL_FSM val and check if condition on val exist 1172 IDLE_CHK_1(0x1C, IGU_REG_SB_CTRL_FSM, (val != 0), IDLE_CHK_WARNING, "IGU: block is not in idle. SB_CTRL_FSM should be zero in idle state"); 1173 // Read register IGU_REG_INT_HANDLE_FSM val and check if condition on val exist 1174 IDLE_CHK_1(0x1C, IGU_REG_INT_HANDLE_FSM, (val != 0), IDLE_CHK_WARNING, "IGU: block is not in idle. INT_HANDLE_FSM should be zero in idle state"); 1175 // Read register IGU_REG_ATTN_FSM val and check if condition on val exist 1176 IDLE_CHK_1(0x1C, IGU_REG_ATTN_FSM, ((val & ~0x2) != 0), IDLE_CHK_WARNING, "IGU: block is not in idle. SB_ATTN_FSMshould be zeroor two in idle state"); 1177 // Read register IGU_REG_CTRL_FSM val and check if condition on val exist 1178 IDLE_CHK_1(0x1C, IGU_REG_CTRL_FSM, ((val & ~0x1) != 0), IDLE_CHK_WARNING, "IGU: block is not in idle. SB_CTRL_FSM should be zero in idle state"); 1179 // Read register IGU_REG_PXP_ARB_FSM val and check if condition on val exist 1180 IDLE_CHK_1(0x1C, IGU_REG_PXP_ARB_FSM, ((val & ~0x1) != 0), IDLE_CHK_WARNING, "IGU: block is not in idle. SB_ARB_FSM should be zero in idle state"); 1181 // Read register IGU_REG_PENDING_BITS_STATUS val and check if condition on val exist 1182 IDLE_CHK_1(0x1C, IGU_REG_PENDING_BITS_STATUS, (val != 0), IDLE_CHK_WARNING, "IGU: block is not in idle. There are pending write done"); 1183 // Read register QM_REG_VOQCREDIT_0 val1 and register QM_REG_VOQINITCREDIT_0 val2 and check if condition on val1,val2 exist 1184 IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_0, QM_REG_VOQINITCREDIT_0, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_0, VOQ credit is not equal to initial credit"); 1185 // Read register QM_REG_VOQCREDIT_1 val1 and register QM_REG_VOQINITCREDIT_1 val2 and check if condition on val1,val2 exist 1186 IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_1, QM_REG_VOQINITCREDIT_1, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_1, VOQ credit is not equal to initial credit"); 1187 // Read register QM_REG_VOQCREDIT_2 val1 and register QM_REG_VOQINITCREDIT_2 val2 and check if condition on val1,val2 exist 1188 IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_2, QM_REG_VOQINITCREDIT_2, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_2, VOQ credit is not equal to initial credit"); 1189 // Read register QM_REG_VOQCREDIT_3 val1 and register QM_REG_VOQINITCREDIT_3 val2 and check if condition on val1,val2 exist 1190 IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_3, QM_REG_VOQINITCREDIT_3, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_3, VOQ credit is not equal to initial credit"); 1191 // Read register QM_REG_VOQCREDIT_4 val1 and register QM_REG_VOQINITCREDIT_4 val2 and check if condition on val1,val2 exist 1192 IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_4, QM_REG_VOQINITCREDIT_4, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_4, VOQ credit is not equal to initial credit"); 1193 // Read register QM_REG_VOQCREDIT_5 val1 and register QM_REG_VOQINITCREDIT_5 val2 and check if condition on val1,val2 exist 1194 IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_5, QM_REG_VOQINITCREDIT_5, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_5, VOQ credit is not equal to initial credit"); 1195 // Read register QM_REG_VOQCREDIT_6 val1 and register QM_REG_VOQINITCREDIT_6 val2 and check if condition on val1,val2 exist 1196 IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_6, QM_REG_VOQINITCREDIT_6, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_6 (LB VOQ), VOQ credit is not equal to initial credit"); 1197 // Read register QM_REG_BYTECRD0 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1198 IDLE_CHK_3(0x10, QM_REG_BYTECRD0, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 0 is not equal to initial credit"); 1199 // Read register QM_REG_BYTECRD1 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1200 IDLE_CHK_3(0x10, QM_REG_BYTECRD1, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 1 is not equal to initial credit"); 1201 // Read register QM_REG_BYTECRD2 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1202 IDLE_CHK_3(0x10, QM_REG_BYTECRD2, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 2 is not equal to initial credit"); 1203 // Read register QM_REG_BYTECRD3 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1204 IDLE_CHK_3(0x10, QM_REG_BYTECRD3, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 3 is not equal to initial credit"); 1205 // Read register QM_REG_BYTECRD4 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1206 IDLE_CHK_3(0x10, QM_REG_BYTECRD4, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 4 is not equal to initial credit"); 1207 // Read register QM_REG_BYTECRD5 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1208 IDLE_CHK_3(0x10, QM_REG_BYTECRD5, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 5 is not equal to initial credit"); 1209 // Read register QM_REG_BYTECRD6 val1 and register QM_REG_BYTECRDINITVAL val2 and check if condition on val1,val2 exist 1210 IDLE_CHK_3(0x10, QM_REG_BYTECRD6, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 6 is not equal to initial credit"); 1211 // Read register QM_REG_FWVOQ0TOHWVOQ val and check if condition on val exist 1212 IDLE_CHK_1(0x10, QM_REG_FWVOQ0TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq0 is mapped to HwVoq7 (non-TX HwVoq)"); 1213 // Read register QM_REG_FWVOQ1TOHWVOQ val and check if condition on val exist 1214 IDLE_CHK_1(0x10, QM_REG_FWVOQ1TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq1 is mapped to HwVoq7 (non-TX HwVoq)"); 1215 // Read register QM_REG_FWVOQ2TOHWVOQ val and check if condition on val exist 1216 IDLE_CHK_1(0x10, QM_REG_FWVOQ2TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq2 is mapped to HwVoq7 (non-TX HwVoq)"); 1217 // Read register QM_REG_FWVOQ3TOHWVOQ val and check if condition on val exist 1218 IDLE_CHK_1(0x10, QM_REG_FWVOQ3TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq3 is mapped to HwVoq7 (non-TX HwVoq)"); 1219 // Read register QM_REG_FWVOQ4TOHWVOQ val and check if condition on val exist 1220 IDLE_CHK_1(0x10, QM_REG_FWVOQ4TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq4 is mapped to HwVoq7 (non-TX HwVoq)"); 1221 // Read register QM_REG_FWVOQ5TOHWVOQ val and check if condition on val exist 1222 IDLE_CHK_1(0x10, QM_REG_FWVOQ5TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq5 is mapped to HwVoq7 (non-TX HwVoq)"); 1223 // Read register QM_REG_FWVOQ6TOHWVOQ val and check if condition on val exist 1224 IDLE_CHK_1(0x10, QM_REG_FWVOQ6TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq6 is mapped to HwVoq7 (non-TX HwVoq)"); 1225 // Read register QM_REG_FWVOQ7TOHWVOQ val and check if condition on val exist 1226 IDLE_CHK_1(0x10, QM_REG_FWVOQ7TOHWVOQ, (val == 0x7), IDLE_CHK_ERROR, "QM: FwVoq7 is mapped to HwVoq7 (non-TX HwVoq)"); 1227 // Read register NIG_REG_INGRESS_EOP_PORT0_EMPTY val and check if condition on val exist 1228 IDLE_CHK_1(0x1F, NIG_REG_INGRESS_EOP_PORT0_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 EOP FIFO is not empty."); 1229 // Read register NIG_REG_INGRESS_EOP_PORT1_EMPTY val and check if condition on val exist 1230 IDLE_CHK_1(0x1F, NIG_REG_INGRESS_EOP_PORT1_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 EOP FIFO is not empty."); 1231 // Read register NIG_REG_INGRESS_EOP_LB_EMPTY val and check if condition on val exist 1232 IDLE_CHK_1(0x1F, NIG_REG_INGRESS_EOP_LB_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: LB EOP FIFO is not empty."); 1233 // Read register NIG_REG_INGRESS_RMP0_DSCR_EMPTY val and check if condition on val exist 1234 IDLE_CHK_1(0x1F, NIG_REG_INGRESS_RMP0_DSCR_EMPTY, (val != 1), IDLE_CHK_WARNING, "NIG: Port 0 RX MCP descriptor FIFO is not empty."); 1235 // Read register NIG_REG_INGRESS_RMP1_DSCR_EMPTY val and check if condition on val exist 1236 IDLE_CHK_1(0x1F, NIG_REG_INGRESS_RMP1_DSCR_EMPTY, (val != 1), IDLE_CHK_WARNING, "NIG: Port 1 RX MCP descriptor FIFO is not empty."); 1237 // Read register NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY val and check if condition on val exist 1238 IDLE_CHK_1(0x1F, NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF LB FIFO is not empty."); 1239 // Read register NIG_REG_EGRESS_MNG0_FIFO_EMPTY val and check if condition on val exist 1240 IDLE_CHK_1(0x1F, NIG_REG_EGRESS_MNG0_FIFO_EMPTY, (val != 1), IDLE_CHK_WARNING, "NIG: Port 0 TX MCP FIFO is not empty."); 1241 // Read register NIG_REG_EGRESS_MNG1_FIFO_EMPTY val and check if condition on val exist 1242 IDLE_CHK_1(0x1F, NIG_REG_EGRESS_MNG1_FIFO_EMPTY, (val != 1), IDLE_CHK_WARNING, "NIG: Port 1 TX MCP FIFO is not empty."); 1243 // Read register NIG_REG_EGRESS_DEBUG_FIFO_EMPTY val and check if condition on val exist 1244 IDLE_CHK_1(0x1F, NIG_REG_EGRESS_DEBUG_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Debug FIFO is not empty."); 1245 // Read register NIG_REG_EGRESS_DELAY0_EMPTY val and check if condition on val exist 1246 IDLE_CHK_1(0x1F, NIG_REG_EGRESS_DELAY0_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF0 FIFO is not empty."); 1247 // Read register NIG_REG_EGRESS_DELAY1_EMPTY val and check if condition on val exist 1248 IDLE_CHK_1(0x1F, NIG_REG_EGRESS_DELAY1_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF1 FIFO is not empty."); 1249 // Read register NIG_REG_LLH0_FIFO_EMPTY val and check if condition on val exist 1250 IDLE_CHK_1(0x1F, NIG_REG_LLH0_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 RX LLH FIFO is not empty."); 1251 // Read register NIG_REG_LLH1_FIFO_EMPTY val and check if condition on val exist 1252 IDLE_CHK_1(0x1F, NIG_REG_LLH1_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 RX LLH FIFO is not empty."); 1253 // Read register NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY val and check if condition on val exist 1254 IDLE_CHK_1(0x1C, NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY, (val != 1), IDLE_CHK_WARNING, "NIG: Port 0 TX MCP FIFO for traffic going to the host is not empty."); 1255 // Read register NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY val and check if condition on val exist 1256 IDLE_CHK_1(0x1C, NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY, (val != 1), IDLE_CHK_WARNING, "NIG: Port 1 TX MCP FIFO for traffic going to the host is not empty."); 1257 // Read register NIG_REG_P0_TLLH_FIFO_EMPTY val and check if condition on val exist 1258 IDLE_CHK_1(0x1C, NIG_REG_P0_TLLH_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 TX LLH FIFO is not empty."); 1259 // Read register NIG_REG_P1_TLLH_FIFO_EMPTY val and check if condition on val exist 1260 IDLE_CHK_1(0x1C, NIG_REG_P1_TLLH_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 TX LLH FIFO is not empty."); 1261 // Read register NIG_REG_P0_HBUF_DSCR_EMPTY val and check if condition on val exist 1262 IDLE_CHK_1(0x1C, NIG_REG_P0_HBUF_DSCR_EMPTY, (val != 1), IDLE_CHK_WARNING, "NIG: Port 0 RX MCP descriptor FIFO for traffic from the host is not empty."); 1263 // Read register NIG_REG_P1_HBUF_DSCR_EMPTY val and check if condition on val exist 1264 IDLE_CHK_1(0x1C, NIG_REG_P1_HBUF_DSCR_EMPTY, (val != 1), IDLE_CHK_WARNING, "NIG: Port 1 RX MCP descriptor FIFO for traffic from the host is not empty."); 1265 // Read register NIG_REG_P0_RX_MACFIFO_EMPTY val and check if condition on val exist 1266 IDLE_CHK_1(0x18, NIG_REG_P0_RX_MACFIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 RX MAC interface FIFO is not empty."); 1267 // Read register NIG_REG_P1_RX_MACFIFO_EMPTY val and check if condition on val exist 1268 IDLE_CHK_1(0x18, NIG_REG_P1_RX_MACFIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 RX MAC interface FIFO is not empty."); 1269 // Read register NIG_REG_P0_TX_MACFIFO_EMPTY val and check if condition on val exist 1270 IDLE_CHK_1(0x18, NIG_REG_P0_TX_MACFIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 TX MAC interface FIFO is not empty."); 1271 // Read register NIG_REG_P1_TX_MACFIFO_EMPTY val and check if condition on val exist 1272 IDLE_CHK_1(0x18, NIG_REG_P1_TX_MACFIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 TX MAC interface FIFO is not empty."); 1273 // Read register NIG_REG_EGRESS_DELAY2_EMPTY val and check if condition on val exist 1274 IDLE_CHK_1(0x10, NIG_REG_EGRESS_DELAY2_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF2 FIFO is not empty."); 1275 // Read register NIG_REG_EGRESS_DELAY3_EMPTY val and check if condition on val exist 1276 IDLE_CHK_1(0x10, NIG_REG_EGRESS_DELAY3_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF3 FIFO is not empty."); 1277 // Read register NIG_REG_EGRESS_DELAY4_EMPTY val and check if condition on val exist 1278 IDLE_CHK_1(0x10, NIG_REG_EGRESS_DELAY4_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF4 FIFO is not empty."); 1279 // Read register NIG_REG_EGRESS_DELAY5_EMPTY val and check if condition on val exist 1280 IDLE_CHK_1(0x10, NIG_REG_EGRESS_DELAY5_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF5 FIFO is not empty."); 1281 1282 // Check if there were errors 1283 if (errors == 0) { 1284 DbgMessage(pdev, FATAL, "Idle_chk completed successfully (with %d warnings of %d checks)\n", warnings, total); 1285 } else { 1286 DbgMessage(pdev, FATAL, "Idle_chk failed !!! (with %d errors, %d warnings of %d checks)\n",errors, warnings, total); 1287 } 1288 // Re-enable timers 1289 if (is_enable_timer0) { 1290 lm_enable_timer(pdev,0); 1291 } 1292 if (is_enable_timer1) { 1293 lm_enable_timer(pdev,1); 1294 } 1295 return errors; 1296 } 1297 // This code section is for WinDbg Extension (b10kd) 1298 #if defined(_B10KD_EXT) 1299 #pragma warning( default : 4242 4244 ) 1300 #endif // _B10KD_EXT 1301