1 2 /***************************************************************************** 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 * 22 * Copyright 2014 QLogic Corporation 23 * The contents of this file are subject to the terms of the 24 * QLogic End User License (the "License"). 25 * You may not use this file except in compliance with the License. 26 * 27 * You can obtain a copy of the License at 28 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/ 29 * QLogic_End_User_Software_License.txt 30 * See the License for the specific language governing permissions 31 * and limitations under the License. 32 * 33 *****************************************************************************/ 34 35 #include "sync.h" 36 #include "lm5710.h" 37 38 #ifndef UEFI64 39 typedef u32_t mm_int_ptr_t; 40 #else 41 typedef u64_t mm_int_ptr_t; 42 #endif 43 44 typedef int mm_spin_lock_t; 45 46 #define mm_read_barrier_imp() 47 #define mm_write_barrier_imp() 48 #define mm_barrier_imp() 49 50 static __inline void mm_atomic_set_imp(u32_t *p, u32_t v) 51 { 52 LOCK(); 53 *p = v; 54 UNLOCK(); 55 } 56 57 static __inline s32_t mm_atomic_dec_imp(u32_t *p) 58 { 59 s32_t ret; 60 LOCK(); 61 ret = --(*p); 62 UNLOCK(); 63 return ret; 64 } 65 66 static __inline s32_t mm_atomic_inc_imp(u32_t *p) 67 { 68 s32_t ret; 69 LOCK(); 70 ret = ++(*p); 71 UNLOCK(); 72 return ret; 73 } 74 75 static __inline s32_t mm_atomic_and_imp(u32_t *p, u32_t v) 76 { 77 s32_t ret; 78 LOCK(); 79 ret = *p; 80 *p &= v; 81 UNLOCK(); 82 return ret; 83 } 84 85 static __inline unsigned long mm_atomic_long_and_imp(unsigned long *p, 86 unsigned long v) 87 { 88 unsigned long ret; 89 LOCK(); 90 ret = *p; 91 *p &= v; 92 UNLOCK(); 93 return ret; 94 } 95 96 static __inline s32_t mm_atomic_or_imp(u32_t *p, u32_t v) 97 { 98 s32_t ret; 99 LOCK(); 100 ret = *p; 101 *p |= v; 102 UNLOCK(); 103 return ret; 104 } 105 106 static __inline unsigned long mm_atomic_long_or_imp(unsigned long *p, 107 unsigned long v) 108 { 109 unsigned long ret; 110 LOCK(); 111 ret = *p; 112 *p |= v; 113 UNLOCK(); 114 return ret; 115 } 116 117 #define mm_atomic_read_imp(_p) (*_p) 118 #define mm_atomic_long_read_imp(_p) (*_p) 119 120 static __inline s32_t mm_atomic_cmpxchg_imp(u32_t *p, 121 u32_t old_v, 122 u32_t new_v) 123 { 124 s32_t ret; 125 LOCK(); 126 ret = *p; 127 if (*p == old_v) 128 { 129 *p = new_v; 130 } 131 UNLOCK(); 132 return ret; 133 } 134 135 136 #define MM_WRITE_DOORBELL_IMP(PDEV, BAR, CID, VAL) \ 137 LM_BAR_WR32_OFFSET((PDEV), BAR_1, (u32_t)((int_ptr_t)((u8_t *)(PDEV)->context_info->array[CID].cid_resc.mapped_cid_bar_addr - \ 138 (PDEV)->hw_info.mem_base[BAR_1].as_u64 + (DPM_TRIGER_TYPE))), (VAL)) 139 140 #define MM_REGISTER_LPME_IMP(_pdev, _func, _b_fw_access, _b_queue_for_fw) \ 141 (LM_STATUS_SUCCESS) 142 143 144 #define MM_ACQUIRE_SPQ_LOCK_IMP(pdev) LOCK() 145 #define MM_RELEASE_SPQ_LOCK_IMP(pdev) UNLOCK() 146 #define MM_ACQUIRE_SPQ_LOCK_DPC_IMP(pdev) LOCK() 147 #define MM_RELEASE_SPQ_LOCK_DPC_IMP(pdev) UNLOCK() 148 149 #define MM_ACQUIRE_CID_LOCK_IMP(pdev) LOCK() 150 #define MM_RELEASE_CID_LOCK_IMP(pdev) UNLOCK() 151 152 #define MM_ACQUIRE_REQUEST_LOCK_IMP(pdev) LOCK() 153 #define MM_RELEASE_REQUEST_LOCK_IMP(pdev) UNLOCK() 154 155 #define MM_ACQUIRE_PHY_LOCK_IMP(pdev) LOCK() 156 #define MM_RELEASE_PHY_LOCK_IMP(pdev) UNLOCK() 157 #define MM_ACQUIRE_PHY_LOCK_DPC_IMP(pdev) LOCK() 158 #define MM_RELEASE_PHY_LOCK_DPC_IMP(pdev) UNLOCK() 159 160 #define MM_ACQUIRE_MCP_LOCK_IMP(pdev) LOCK() 161 #define MM_RELEASE_MCP_LOCK_IMP(pdev) UNLOCK() 162 163 #define MM_ACQUIRE_ISLES_CONTROL_LOCK_IMP(pdev) LOCK() 164 #define MM_RELEASE_ISLES_CONTROL_LOCK_IMP(pdev) UNLOCK() 165 #define MM_ACQUIRE_ISLES_CONTROL_LOCK_DPC_IMP(pdev) LOCK() 166 #define MM_RELEASE_ISLES_CONTROL_LOCK_DPC_IMP(pdev) UNLOCK() 167 168 #define MM_ACQUIRE_IND_REG_LOCK_IMP(pdev) LOCK() 169 #define MM_RELEASE_IND_REG_LOCK_IMP(pdev) UNLOCK() 170 171 #define MM_ACQUIRE_RAMROD_COMP_LOCK_IMP(_pdev) LOCK() 172 #define MM_RELEASE_RAMROD_COMP_LOCK_IMP(_pdev) UNLOCK() 173 174 #define MM_ACQUIRE_LOADER_LOCK_IMP() LOCK() 175 #define MM_RELEASE_LOADER_LOCK_IMP() UNLOCK() 176 177 #define MM_ACQUIRE_SP_REQ_MGR_LOCK_IMP(pdev) LOCK() 178 #define MM_RELEASE_SP_REQ_MGR_LOCK_IMP(pdev) UNLOCK() 179 180 #define MM_ACQUIRE_SB_LOCK_IMP(pdev, sb_idx) LOCK() 181 #define MM_RELEASE_SB_LOCK_IMP(pdev, sb_idx) UNLOCK() 182 183 #define MM_ACQUIRE_ETH_CON_LOCK_IMP(pdev) LOCK() 184 #define MM_RELEASE_ETH_CON_LOCK_IMP(pdev) UNLOCK() 185 186 #ifdef VF_INVOLVED 187 188 #define MM_ACQUIRE_PF_LOCK_IMP(pdev) LOCK() 189 #define MM_RELEASE_PF_LOCK_IMP(pdev) UNLOCK() 190 191 #define MM_ACQUIRE_VFS_STATS_LOCK_IMP(pdev) LOCK() 192 #define MM_RELEASE_VFS_STATS_LOCK_IMP(pdev) UNLOCK() 193 #define MM_ACQUIRE_VFS_STATS_LOCK_DPC_IMP(pdev) LOCK() 194 #define MM_RELEASE_VFS_STATS_LOCK_DPC_IMP(pdev) UNLOCK() 195 196 #endif /* VF_INVOLVED */ 197 198 static __inline void mm_init_lock(struct _lm_device_t *_pdev, 199 mm_spin_lock_t *lock) 200 { 201 /* Do nothing */ 202 } 203 204 static __inline lm_status_t mm_acquire_lock(mm_spin_lock_t *spinlock) 205 { 206 LOCK(); 207 return LM_STATUS_SUCCESS; 208 } 209 210 static __inline lm_status_t mm_release_lock(mm_spin_lock_t *spinlock) 211 { 212 UNLOCK(); 213 return LM_STATUS_SUCCESS; 214 } 215 216 217 218 219 220 221 #define mm_er_initiate_recovery_imp(pdev) \ 222 (LM_STATUS_FAILURE) 223 224 #define mm_register_dpc_imp(_pdev, _func) \ 225 (LM_STATUS_FAILURE) 226 227 #define mm_empty_ramrod_received_imp(pdev, empty_data) 228 229 #define mm_dbus_start_if_enabled_imp(pdev) 230 #define mm_dbus_stop_if_started_imp(pdev) 231 232 #ifdef BIG_ENDIAN 233 // LE 234 #define mm_le16_to_cpu_imp(val) SWAP_BYTES16(val) 235 #define mm_cpu_to_le16_imp(val) SWAP_BYTES16(val) 236 #define mm_le32_to_cpu_imp(val) SWAP_BYTES32(val) 237 #define mm_cpu_to_le32_imp(val) SWAP_BYTES32(val) 238 // BE 239 #define mm_be32_to_cpu_imp(val) (val) 240 #define mm_cpu_to_be32_imp(val) (val) 241 #define mm_be16_to_cpu_imp(val) (val) 242 #define mm_cpu_to_be16_imp(val) (val) 243 #else /* LITTLE_ENDIAN */ 244 // LE 245 #define mm_le16_to_cpu_imp(val) (val) 246 #define mm_cpu_to_le16_imp(val) (val) 247 #define mm_le32_to_cpu_imp(val) (val) 248 #define mm_cpu_to_le32_imp(val) (val) 249 // BE 250 #define mm_be32_to_cpu_imp(val) SWAP_BYTES32(val) 251 #define mm_cpu_to_be32_imp(val) SWAP_BYTES32(val) 252 #define mm_be16_to_cpu_imp(val) SWAP_BYTES16(val) 253 #define mm_cpu_to_be16_imp(val) SWAP_BYTES16(val) 254 #endif /* ifdef BIG_ENDIAN */ 255 256 257 #define mm_get_bar_offset_imp(pdev, bar_num, bar_addr) \ 258 lm_get_bar_offset_direct(pdev, bar_num, bar_addr) 259 260 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ 261 lm_get_bar_size_direct(pdev, bar_num, val_p) 262 263 #define MM_DCB_MP_L2_IS_ENABLE(_pdev) (FALSE) 264 265 void mm_bar_read_byte(struct _lm_device_t *pdev, 266 u8_t bar, 267 u32_t offset, 268 u8_t *ret); 269 270 void mm_bar_read_word(struct _lm_device_t *pdev, 271 u8_t bar, 272 u32_t offset, 273 u16_t *ret); 274 275 void mm_bar_read_dword(struct _lm_device_t *pdev, 276 u8_t bar, 277 u32_t offset, 278 u32_t *ret); 279 280 void mm_bar_read_ddword(struct _lm_device_t *pdev, 281 u8_t bar, 282 u32_t offset, 283 u64_t *ret); 284 285 void mm_bar_write_byte(struct _lm_device_t *pdev, 286 u8_t bar, 287 u32_t offset, 288 u8_t val); 289 290 void mm_bar_write_word(struct _lm_device_t *pdev, 291 u8_t bar, 292 u32_t offset, 293 u16_t val); 294 295 void mm_bar_write_dword(struct _lm_device_t *pdev, 296 u8_t bar, 297 u32_t offset, 298 u32_t val); 299 300 void mm_bar_write_ddword(struct _lm_device_t *pdev, 301 u8_t bar, 302 u32_t offset, 303 u64_t val); 304 305 void mm_bar_copy_buffer( 306 struct _lm_device_t * _pdev, 307 u8_t bar, 308 u32_t offset, 309 u32_t size, 310 u32_t *buf_ptr 311 ); 312 313 u32_t mm_get_wol_flags( IN struct _lm_device_t* pdev ); 314 315 u32_t mm_get_feature_flags(struct _lm_device_t* pdev); 316 317 u32_t mm_get_vmq_cnt(struct _lm_device_t* pdev); 318 319 lm_status_t mm_i2c_update(struct _lm_device_t *pdev); 320 321 u64_t mm_query_system_time(void); 322