1[ 2 { 3 "EventCode": "0x14", 4 "UMask": "0x1", 5 "EventName": "ARITH.CYCLES_DIV_BUSY", 6 "BriefDescription": "Cycles the divider is busy", 7 "PublicDescription": "Cycles the divider is busy", 8 "Counter": "0,1,2,3", 9 "SampleAfterValue": "2000000", 10 "MSRIndex": "0", 11 "MSRValue": "0", 12 "CounterMask": "0", 13 "Invert": "0", 14 "AnyThread": "0", 15 "EdgeDetect": "0", 16 "PEBS": "0", 17 "Offcore": "0" 18 }, 19 { 20 "EventCode": "0x14", 21 "UMask": "0x1", 22 "EventName": "ARITH.DIV", 23 "BriefDescription": "Divide Operations executed", 24 "PublicDescription": "Divide Operations executed", 25 "Counter": "0,1,2,3", 26 "SampleAfterValue": "2000000", 27 "MSRIndex": "0", 28 "MSRValue": "0", 29 "CounterMask": "1", 30 "Invert": "1", 31 "AnyThread": "0", 32 "EdgeDetect": "1", 33 "PEBS": "0", 34 "Offcore": "0" 35 }, 36 { 37 "EventCode": "0x14", 38 "UMask": "0x2", 39 "EventName": "ARITH.MUL", 40 "BriefDescription": "Multiply operations executed", 41 "PublicDescription": "Multiply operations executed", 42 "Counter": "0,1,2,3", 43 "SampleAfterValue": "2000000", 44 "MSRIndex": "0", 45 "MSRValue": "0", 46 "CounterMask": "0", 47 "Invert": "0", 48 "AnyThread": "0", 49 "EdgeDetect": "0", 50 "PEBS": "0", 51 "Offcore": "0" 52 }, 53 { 54 "EventCode": "0xE6", 55 "UMask": "0x2", 56 "EventName": "BACLEAR.BAD_TARGET", 57 "BriefDescription": "BACLEAR asserted with bad target address", 58 "PublicDescription": "BACLEAR asserted with bad target address", 59 "Counter": "0,1,2,3", 60 "SampleAfterValue": "2000000", 61 "MSRIndex": "0", 62 "MSRValue": "0", 63 "CounterMask": "0", 64 "Invert": "0", 65 "AnyThread": "0", 66 "EdgeDetect": "0", 67 "PEBS": "0", 68 "Offcore": "0" 69 }, 70 { 71 "EventCode": "0xE6", 72 "UMask": "0x1", 73 "EventName": "BACLEAR.CLEAR", 74 "BriefDescription": "BACLEAR asserted, regardless of cause ", 75 "PublicDescription": "BACLEAR asserted, regardless of cause ", 76 "Counter": "0,1,2,3", 77 "SampleAfterValue": "2000000", 78 "MSRIndex": "0", 79 "MSRValue": "0", 80 "CounterMask": "0", 81 "Invert": "0", 82 "AnyThread": "0", 83 "EdgeDetect": "0", 84 "PEBS": "0", 85 "Offcore": "0" 86 }, 87 { 88 "EventCode": "0xA7", 89 "UMask": "0x1", 90 "EventName": "BACLEAR_FORCE_IQ", 91 "BriefDescription": "Instruction queue forced BACLEAR", 92 "PublicDescription": "Instruction queue forced BACLEAR", 93 "Counter": "0,1,2,3", 94 "SampleAfterValue": "2000000", 95 "MSRIndex": "0", 96 "MSRValue": "0", 97 "CounterMask": "0", 98 "Invert": "0", 99 "AnyThread": "0", 100 "EdgeDetect": "0", 101 "PEBS": "0", 102 "Offcore": "0" 103 }, 104 { 105 "EventCode": "0xE8", 106 "UMask": "0x1", 107 "EventName": "BPU_CLEARS.EARLY", 108 "BriefDescription": "Early Branch Prediciton Unit clears", 109 "PublicDescription": "Early Branch Prediciton Unit clears", 110 "Counter": "0,1,2,3", 111 "SampleAfterValue": "2000000", 112 "MSRIndex": "0", 113 "MSRValue": "0", 114 "CounterMask": "0", 115 "Invert": "0", 116 "AnyThread": "0", 117 "EdgeDetect": "0", 118 "PEBS": "0", 119 "Offcore": "0" 120 }, 121 { 122 "EventCode": "0xE8", 123 "UMask": "0x2", 124 "EventName": "BPU_CLEARS.LATE", 125 "BriefDescription": "Late Branch Prediction Unit clears", 126 "PublicDescription": "Late Branch Prediction Unit clears", 127 "Counter": "0,1,2,3", 128 "SampleAfterValue": "2000000", 129 "MSRIndex": "0", 130 "MSRValue": "0", 131 "CounterMask": "0", 132 "Invert": "0", 133 "AnyThread": "0", 134 "EdgeDetect": "0", 135 "PEBS": "0", 136 "Offcore": "0" 137 }, 138 { 139 "EventCode": "0xE5", 140 "UMask": "0x1", 141 "EventName": "BPU_MISSED_CALL_RET", 142 "BriefDescription": "Branch prediction unit missed call or return", 143 "PublicDescription": "Branch prediction unit missed call or return", 144 "Counter": "0,1,2,3", 145 "SampleAfterValue": "2000000", 146 "MSRIndex": "0", 147 "MSRValue": "0", 148 "CounterMask": "0", 149 "Invert": "0", 150 "AnyThread": "0", 151 "EdgeDetect": "0", 152 "PEBS": "0", 153 "Offcore": "0" 154 }, 155 { 156 "EventCode": "0xE0", 157 "UMask": "0x1", 158 "EventName": "BR_INST_DECODED", 159 "BriefDescription": "Branch instructions decoded", 160 "PublicDescription": "Branch instructions decoded", 161 "Counter": "0,1,2,3", 162 "SampleAfterValue": "2000000", 163 "MSRIndex": "0", 164 "MSRValue": "0", 165 "CounterMask": "0", 166 "Invert": "0", 167 "AnyThread": "0", 168 "EdgeDetect": "0", 169 "PEBS": "0", 170 "Offcore": "0" 171 }, 172 { 173 "EventCode": "0x88", 174 "UMask": "0x7F", 175 "EventName": "BR_INST_EXEC.ANY", 176 "BriefDescription": "Branch instructions executed", 177 "PublicDescription": "Branch instructions executed", 178 "Counter": "0,1,2,3", 179 "SampleAfterValue": "200000", 180 "MSRIndex": "0", 181 "MSRValue": "0", 182 "CounterMask": "0", 183 "Invert": "0", 184 "AnyThread": "0", 185 "EdgeDetect": "0", 186 "PEBS": "0", 187 "Offcore": "0" 188 }, 189 { 190 "EventCode": "0x88", 191 "UMask": "0x1", 192 "EventName": "BR_INST_EXEC.COND", 193 "BriefDescription": "Conditional branch instructions executed", 194 "PublicDescription": "Conditional branch instructions executed", 195 "Counter": "0,1,2,3", 196 "SampleAfterValue": "200000", 197 "MSRIndex": "0", 198 "MSRValue": "0", 199 "CounterMask": "0", 200 "Invert": "0", 201 "AnyThread": "0", 202 "EdgeDetect": "0", 203 "PEBS": "0", 204 "Offcore": "0" 205 }, 206 { 207 "EventCode": "0x88", 208 "UMask": "0x2", 209 "EventName": "BR_INST_EXEC.DIRECT", 210 "BriefDescription": "Unconditional branches executed", 211 "PublicDescription": "Unconditional branches executed", 212 "Counter": "0,1,2,3", 213 "SampleAfterValue": "200000", 214 "MSRIndex": "0", 215 "MSRValue": "0", 216 "CounterMask": "0", 217 "Invert": "0", 218 "AnyThread": "0", 219 "EdgeDetect": "0", 220 "PEBS": "0", 221 "Offcore": "0" 222 }, 223 { 224 "EventCode": "0x88", 225 "UMask": "0x10", 226 "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", 227 "BriefDescription": "Unconditional call branches executed", 228 "PublicDescription": "Unconditional call branches executed", 229 "Counter": "0,1,2,3", 230 "SampleAfterValue": "20000", 231 "MSRIndex": "0", 232 "MSRValue": "0", 233 "CounterMask": "0", 234 "Invert": "0", 235 "AnyThread": "0", 236 "EdgeDetect": "0", 237 "PEBS": "0", 238 "Offcore": "0" 239 }, 240 { 241 "EventCode": "0x88", 242 "UMask": "0x20", 243 "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", 244 "BriefDescription": "Indirect call branches executed", 245 "PublicDescription": "Indirect call branches executed", 246 "Counter": "0,1,2,3", 247 "SampleAfterValue": "20000", 248 "MSRIndex": "0", 249 "MSRValue": "0", 250 "CounterMask": "0", 251 "Invert": "0", 252 "AnyThread": "0", 253 "EdgeDetect": "0", 254 "PEBS": "0", 255 "Offcore": "0" 256 }, 257 { 258 "EventCode": "0x88", 259 "UMask": "0x4", 260 "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", 261 "BriefDescription": "Indirect non call branches executed", 262 "PublicDescription": "Indirect non call branches executed", 263 "Counter": "0,1,2,3", 264 "SampleAfterValue": "20000", 265 "MSRIndex": "0", 266 "MSRValue": "0", 267 "CounterMask": "0", 268 "Invert": "0", 269 "AnyThread": "0", 270 "EdgeDetect": "0", 271 "PEBS": "0", 272 "Offcore": "0" 273 }, 274 { 275 "EventCode": "0x88", 276 "UMask": "0x30", 277 "EventName": "BR_INST_EXEC.NEAR_CALLS", 278 "BriefDescription": "Call branches executed", 279 "PublicDescription": "Call branches executed", 280 "Counter": "0,1,2,3", 281 "SampleAfterValue": "20000", 282 "MSRIndex": "0", 283 "MSRValue": "0", 284 "CounterMask": "0", 285 "Invert": "0", 286 "AnyThread": "0", 287 "EdgeDetect": "0", 288 "PEBS": "0", 289 "Offcore": "0" 290 }, 291 { 292 "EventCode": "0x88", 293 "UMask": "0x7", 294 "EventName": "BR_INST_EXEC.NON_CALLS", 295 "BriefDescription": "All non call branches executed", 296 "PublicDescription": "All non call branches executed", 297 "Counter": "0,1,2,3", 298 "SampleAfterValue": "200000", 299 "MSRIndex": "0", 300 "MSRValue": "0", 301 "CounterMask": "0", 302 "Invert": "0", 303 "AnyThread": "0", 304 "EdgeDetect": "0", 305 "PEBS": "0", 306 "Offcore": "0" 307 }, 308 { 309 "EventCode": "0x88", 310 "UMask": "0x8", 311 "EventName": "BR_INST_EXEC.RETURN_NEAR", 312 "BriefDescription": "Indirect return branches executed", 313 "PublicDescription": "Indirect return branches executed", 314 "Counter": "0,1,2,3", 315 "SampleAfterValue": "20000", 316 "MSRIndex": "0", 317 "MSRValue": "0", 318 "CounterMask": "0", 319 "Invert": "0", 320 "AnyThread": "0", 321 "EdgeDetect": "0", 322 "PEBS": "0", 323 "Offcore": "0" 324 }, 325 { 326 "EventCode": "0x88", 327 "UMask": "0x40", 328 "EventName": "BR_INST_EXEC.TAKEN", 329 "BriefDescription": "Taken branches executed", 330 "PublicDescription": "Taken branches executed", 331 "Counter": "0,1,2,3", 332 "SampleAfterValue": "200000", 333 "MSRIndex": "0", 334 "MSRValue": "0", 335 "CounterMask": "0", 336 "Invert": "0", 337 "AnyThread": "0", 338 "EdgeDetect": "0", 339 "PEBS": "0", 340 "Offcore": "0" 341 }, 342 { 343 "EventCode": "0xC4", 344 "UMask": "0x4", 345 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 346 "BriefDescription": "Retired branch instructions (Precise Event)", 347 "PublicDescription": "Retired branch instructions (Precise Event)", 348 "Counter": "0,1,2,3", 349 "SampleAfterValue": "200000", 350 "MSRIndex": "0", 351 "MSRValue": "0", 352 "CounterMask": "0", 353 "Invert": "0", 354 "AnyThread": "0", 355 "EdgeDetect": "0", 356 "PEBS": "1", 357 "Offcore": "0" 358 }, 359 { 360 "EventCode": "0xC4", 361 "UMask": "0x1", 362 "EventName": "BR_INST_RETIRED.CONDITIONAL", 363 "BriefDescription": "Retired conditional branch instructions (Precise Event)", 364 "PublicDescription": "Retired conditional branch instructions (Precise Event)", 365 "Counter": "0,1,2,3", 366 "SampleAfterValue": "200000", 367 "MSRIndex": "0", 368 "MSRValue": "0", 369 "CounterMask": "0", 370 "Invert": "0", 371 "AnyThread": "0", 372 "EdgeDetect": "0", 373 "PEBS": "1", 374 "Offcore": "0" 375 }, 376 { 377 "EventCode": "0xC4", 378 "UMask": "0x2", 379 "EventName": "BR_INST_RETIRED.NEAR_CALL", 380 "BriefDescription": "Retired near call instructions (Precise Event)", 381 "PublicDescription": "Retired near call instructions (Precise Event)", 382 "Counter": "0,1,2,3", 383 "SampleAfterValue": "20000", 384 "MSRIndex": "0", 385 "MSRValue": "0", 386 "CounterMask": "0", 387 "Invert": "0", 388 "AnyThread": "0", 389 "EdgeDetect": "0", 390 "PEBS": "1", 391 "Offcore": "0" 392 }, 393 { 394 "EventCode": "0x89", 395 "UMask": "0x7F", 396 "EventName": "BR_MISP_EXEC.ANY", 397 "BriefDescription": "Mispredicted branches executed", 398 "PublicDescription": "Mispredicted branches executed", 399 "Counter": "0,1,2,3", 400 "SampleAfterValue": "20000", 401 "MSRIndex": "0", 402 "MSRValue": "0", 403 "CounterMask": "0", 404 "Invert": "0", 405 "AnyThread": "0", 406 "EdgeDetect": "0", 407 "PEBS": "0", 408 "Offcore": "0" 409 }, 410 { 411 "EventCode": "0x89", 412 "UMask": "0x1", 413 "EventName": "BR_MISP_EXEC.COND", 414 "BriefDescription": "Mispredicted conditional branches executed", 415 "PublicDescription": "Mispredicted conditional branches executed", 416 "Counter": "0,1,2,3", 417 "SampleAfterValue": "20000", 418 "MSRIndex": "0", 419 "MSRValue": "0", 420 "CounterMask": "0", 421 "Invert": "0", 422 "AnyThread": "0", 423 "EdgeDetect": "0", 424 "PEBS": "0", 425 "Offcore": "0" 426 }, 427 { 428 "EventCode": "0x89", 429 "UMask": "0x2", 430 "EventName": "BR_MISP_EXEC.DIRECT", 431 "BriefDescription": "Mispredicted unconditional branches executed", 432 "PublicDescription": "Mispredicted unconditional branches executed", 433 "Counter": "0,1,2,3", 434 "SampleAfterValue": "20000", 435 "MSRIndex": "0", 436 "MSRValue": "0", 437 "CounterMask": "0", 438 "Invert": "0", 439 "AnyThread": "0", 440 "EdgeDetect": "0", 441 "PEBS": "0", 442 "Offcore": "0" 443 }, 444 { 445 "EventCode": "0x89", 446 "UMask": "0x10", 447 "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", 448 "BriefDescription": "Mispredicted non call branches executed", 449 "PublicDescription": "Mispredicted non call branches executed", 450 "Counter": "0,1,2,3", 451 "SampleAfterValue": "2000", 452 "MSRIndex": "0", 453 "MSRValue": "0", 454 "CounterMask": "0", 455 "Invert": "0", 456 "AnyThread": "0", 457 "EdgeDetect": "0", 458 "PEBS": "0", 459 "Offcore": "0" 460 }, 461 { 462 "EventCode": "0x89", 463 "UMask": "0x20", 464 "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", 465 "BriefDescription": "Mispredicted indirect call branches executed", 466 "PublicDescription": "Mispredicted indirect call branches executed", 467 "Counter": "0,1,2,3", 468 "SampleAfterValue": "2000", 469 "MSRIndex": "0", 470 "MSRValue": "0", 471 "CounterMask": "0", 472 "Invert": "0", 473 "AnyThread": "0", 474 "EdgeDetect": "0", 475 "PEBS": "0", 476 "Offcore": "0" 477 }, 478 { 479 "EventCode": "0x89", 480 "UMask": "0x4", 481 "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", 482 "BriefDescription": "Mispredicted indirect non call branches executed", 483 "PublicDescription": "Mispredicted indirect non call branches executed", 484 "Counter": "0,1,2,3", 485 "SampleAfterValue": "2000", 486 "MSRIndex": "0", 487 "MSRValue": "0", 488 "CounterMask": "0", 489 "Invert": "0", 490 "AnyThread": "0", 491 "EdgeDetect": "0", 492 "PEBS": "0", 493 "Offcore": "0" 494 }, 495 { 496 "EventCode": "0x89", 497 "UMask": "0x30", 498 "EventName": "BR_MISP_EXEC.NEAR_CALLS", 499 "BriefDescription": "Mispredicted call branches executed", 500 "PublicDescription": "Mispredicted call branches executed", 501 "Counter": "0,1,2,3", 502 "SampleAfterValue": "2000", 503 "MSRIndex": "0", 504 "MSRValue": "0", 505 "CounterMask": "0", 506 "Invert": "0", 507 "AnyThread": "0", 508 "EdgeDetect": "0", 509 "PEBS": "0", 510 "Offcore": "0" 511 }, 512 { 513 "EventCode": "0x89", 514 "UMask": "0x7", 515 "EventName": "BR_MISP_EXEC.NON_CALLS", 516 "BriefDescription": "Mispredicted non call branches executed", 517 "PublicDescription": "Mispredicted non call branches executed", 518 "Counter": "0,1,2,3", 519 "SampleAfterValue": "20000", 520 "MSRIndex": "0", 521 "MSRValue": "0", 522 "CounterMask": "0", 523 "Invert": "0", 524 "AnyThread": "0", 525 "EdgeDetect": "0", 526 "PEBS": "0", 527 "Offcore": "0" 528 }, 529 { 530 "EventCode": "0x89", 531 "UMask": "0x8", 532 "EventName": "BR_MISP_EXEC.RETURN_NEAR", 533 "BriefDescription": "Mispredicted return branches executed", 534 "PublicDescription": "Mispredicted return branches executed", 535 "Counter": "0,1,2,3", 536 "SampleAfterValue": "2000", 537 "MSRIndex": "0", 538 "MSRValue": "0", 539 "CounterMask": "0", 540 "Invert": "0", 541 "AnyThread": "0", 542 "EdgeDetect": "0", 543 "PEBS": "0", 544 "Offcore": "0" 545 }, 546 { 547 "EventCode": "0x89", 548 "UMask": "0x40", 549 "EventName": "BR_MISP_EXEC.TAKEN", 550 "BriefDescription": "Mispredicted taken branches executed", 551 "PublicDescription": "Mispredicted taken branches executed", 552 "Counter": "0,1,2,3", 553 "SampleAfterValue": "20000", 554 "MSRIndex": "0", 555 "MSRValue": "0", 556 "CounterMask": "0", 557 "Invert": "0", 558 "AnyThread": "0", 559 "EdgeDetect": "0", 560 "PEBS": "0", 561 "Offcore": "0" 562 }, 563 { 564 "EventCode": "0xC5", 565 "UMask": "0x2", 566 "EventName": "BR_MISP_RETIRED.NEAR_CALL", 567 "BriefDescription": "Mispredicted near retired calls (Precise Event)", 568 "PublicDescription": "Mispredicted near retired calls (Precise Event)", 569 "Counter": "0,1,2,3", 570 "SampleAfterValue": "2000", 571 "MSRIndex": "0", 572 "MSRValue": "0", 573 "CounterMask": "0", 574 "Invert": "0", 575 "AnyThread": "0", 576 "EdgeDetect": "0", 577 "PEBS": "1", 578 "Offcore": "0" 579 }, 580 { 581 "EventCode": "0x63", 582 "UMask": "0x2", 583 "EventName": "CACHE_LOCK_CYCLES.L1D", 584 "BriefDescription": "Cycles L1D locked", 585 "PublicDescription": "Cycles L1D locked", 586 "Counter": "0,1", 587 "SampleAfterValue": "2000000", 588 "MSRIndex": "0", 589 "MSRValue": "0", 590 "CounterMask": "0", 591 "Invert": "0", 592 "AnyThread": "0", 593 "EdgeDetect": "0", 594 "PEBS": "0", 595 "Offcore": "0" 596 }, 597 { 598 "EventCode": "0x63", 599 "UMask": "0x1", 600 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 601 "BriefDescription": "Cycles L1D and L2 locked", 602 "PublicDescription": "Cycles L1D and L2 locked", 603 "Counter": "0,1", 604 "SampleAfterValue": "2000000", 605 "MSRIndex": "0", 606 "MSRValue": "0", 607 "CounterMask": "0", 608 "Invert": "0", 609 "AnyThread": "0", 610 "EdgeDetect": "0", 611 "PEBS": "0", 612 "Offcore": "0" 613 }, 614 { 615 "EventCode": "0x0", 616 "UMask": "0x0", 617 "EventName": "CPU_CLK_UNHALTED.REF", 618 "BriefDescription": "Reference cycles when thread is not halted (fixed counter)", 619 "PublicDescription": "Reference cycles when thread is not halted (fixed counter)", 620 "Counter": "Fixed counter 3", 621 "SampleAfterValue": "2000000", 622 "MSRIndex": "0", 623 "MSRValue": "0", 624 "CounterMask": "0", 625 "Invert": "0", 626 "AnyThread": "0", 627 "EdgeDetect": "0", 628 "PEBS": "0", 629 "Offcore": "0" 630 }, 631 { 632 "EventCode": "0x3C", 633 "UMask": "0x1", 634 "EventName": "CPU_CLK_UNHALTED.REF_P", 635 "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 636 "PublicDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 637 "Counter": "0,1,2,3", 638 "SampleAfterValue": "100000", 639 "MSRIndex": "0", 640 "MSRValue": "0", 641 "CounterMask": "0", 642 "Invert": "0", 643 "AnyThread": "0", 644 "EdgeDetect": "0", 645 "PEBS": "0", 646 "Offcore": "0" 647 }, 648 { 649 "EventCode": "0x0", 650 "UMask": "0x0", 651 "EventName": "CPU_CLK_UNHALTED.THREAD", 652 "BriefDescription": "Cycles when thread is not halted (fixed counter)", 653 "PublicDescription": "Cycles when thread is not halted (fixed counter)", 654 "Counter": "Fixed counter 2", 655 "SampleAfterValue": "2000000", 656 "MSRIndex": "0", 657 "MSRValue": "0", 658 "CounterMask": "0", 659 "Invert": "0", 660 "AnyThread": "0", 661 "EdgeDetect": "0", 662 "PEBS": "0", 663 "Offcore": "0" 664 }, 665 { 666 "EventCode": "0x3C", 667 "UMask": "0x0", 668 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 669 "BriefDescription": "Cycles when thread is not halted (programmable counter)", 670 "PublicDescription": "Cycles when thread is not halted (programmable counter)", 671 "Counter": "0,1,2,3", 672 "SampleAfterValue": "2000000", 673 "MSRIndex": "0", 674 "MSRValue": "0", 675 "CounterMask": "0", 676 "Invert": "0", 677 "AnyThread": "0", 678 "EdgeDetect": "0", 679 "PEBS": "0", 680 "Offcore": "0" 681 }, 682 { 683 "EventCode": "0x3C", 684 "UMask": "0x0", 685 "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", 686 "BriefDescription": "Total CPU cycles", 687 "PublicDescription": "Total CPU cycles", 688 "Counter": "0,1,2,3", 689 "SampleAfterValue": "2000000", 690 "MSRIndex": "0", 691 "MSRValue": "0", 692 "CounterMask": "2", 693 "Invert": "1", 694 "AnyThread": "0", 695 "EdgeDetect": "0", 696 "PEBS": "0", 697 "Offcore": "0" 698 }, 699 { 700 "EventCode": "0x8", 701 "UMask": "0x1", 702 "EventName": "DTLB_LOAD_MISSES.ANY", 703 "BriefDescription": "DTLB load misses", 704 "PublicDescription": "DTLB load misses", 705 "Counter": "0,1,2,3", 706 "SampleAfterValue": "200000", 707 "MSRIndex": "0", 708 "MSRValue": "0", 709 "CounterMask": "0", 710 "Invert": "0", 711 "AnyThread": "0", 712 "EdgeDetect": "0", 713 "PEBS": "0", 714 "Offcore": "0" 715 }, 716 { 717 "EventCode": "0x8", 718 "UMask": "0x20", 719 "EventName": "DTLB_LOAD_MISSES.PDE_MISS", 720 "BriefDescription": "DTLB load miss caused by low part of address", 721 "PublicDescription": "DTLB load miss caused by low part of address", 722 "Counter": "0,1,2,3", 723 "SampleAfterValue": "200000", 724 "MSRIndex": "0", 725 "MSRValue": "0", 726 "CounterMask": "0", 727 "Invert": "0", 728 "AnyThread": "0", 729 "EdgeDetect": "0", 730 "PEBS": "0", 731 "Offcore": "0" 732 }, 733 { 734 "EventCode": "0x8", 735 "UMask": "0x10", 736 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 737 "BriefDescription": "DTLB second level hit", 738 "PublicDescription": "DTLB second level hit", 739 "Counter": "0,1,2,3", 740 "SampleAfterValue": "2000000", 741 "MSRIndex": "0", 742 "MSRValue": "0", 743 "CounterMask": "0", 744 "Invert": "0", 745 "AnyThread": "0", 746 "EdgeDetect": "0", 747 "PEBS": "0", 748 "Offcore": "0" 749 }, 750 { 751 "EventCode": "0x8", 752 "UMask": "0x2", 753 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 754 "BriefDescription": "DTLB load miss page walks complete", 755 "PublicDescription": "DTLB load miss page walks complete", 756 "Counter": "0,1,2,3", 757 "SampleAfterValue": "200000", 758 "MSRIndex": "0", 759 "MSRValue": "0", 760 "CounterMask": "0", 761 "Invert": "0", 762 "AnyThread": "0", 763 "EdgeDetect": "0", 764 "PEBS": "0", 765 "Offcore": "0" 766 }, 767 { 768 "EventCode": "0x49", 769 "UMask": "0x1", 770 "EventName": "DTLB_MISSES.ANY", 771 "BriefDescription": "DTLB misses", 772 "PublicDescription": "DTLB misses", 773 "Counter": "0,1,2,3", 774 "SampleAfterValue": "200000", 775 "MSRIndex": "0", 776 "MSRValue": "0", 777 "CounterMask": "0", 778 "Invert": "0", 779 "AnyThread": "0", 780 "EdgeDetect": "0", 781 "PEBS": "0", 782 "Offcore": "0" 783 }, 784 { 785 "EventCode": "0x49", 786 "UMask": "0x10", 787 "EventName": "DTLB_MISSES.STLB_HIT", 788 "BriefDescription": "DTLB first level misses but second level hit", 789 "PublicDescription": "DTLB first level misses but second level hit", 790 "Counter": "0,1,2,3", 791 "SampleAfterValue": "200000", 792 "MSRIndex": "0", 793 "MSRValue": "0", 794 "CounterMask": "0", 795 "Invert": "0", 796 "AnyThread": "0", 797 "EdgeDetect": "0", 798 "PEBS": "0", 799 "Offcore": "0" 800 }, 801 { 802 "EventCode": "0x49", 803 "UMask": "0x2", 804 "EventName": "DTLB_MISSES.WALK_COMPLETED", 805 "BriefDescription": "DTLB miss page walks", 806 "PublicDescription": "DTLB miss page walks", 807 "Counter": "0,1,2,3", 808 "SampleAfterValue": "200000", 809 "MSRIndex": "0", 810 "MSRValue": "0", 811 "CounterMask": "0", 812 "Invert": "0", 813 "AnyThread": "0", 814 "EdgeDetect": "0", 815 "PEBS": "0", 816 "Offcore": "0" 817 }, 818 { 819 "EventCode": "0xD5", 820 "UMask": "0x1", 821 "EventName": "ES_REG_RENAMES", 822 "BriefDescription": "ES segment renames", 823 "PublicDescription": "ES segment renames", 824 "Counter": "0,1,2,3", 825 "SampleAfterValue": "2000000", 826 "MSRIndex": "0", 827 "MSRValue": "0", 828 "CounterMask": "0", 829 "Invert": "0", 830 "AnyThread": "0", 831 "EdgeDetect": "0", 832 "PEBS": "0", 833 "Offcore": "0" 834 }, 835 { 836 "EventCode": "0xF7", 837 "UMask": "0x1", 838 "EventName": "FP_ASSIST.ALL", 839 "BriefDescription": "X87 Floating point assists (Precise Event)", 840 "PublicDescription": "X87 Floating point assists (Precise Event)", 841 "Counter": "0,1,2,3", 842 "SampleAfterValue": "20000", 843 "MSRIndex": "0", 844 "MSRValue": "0", 845 "CounterMask": "0", 846 "Invert": "0", 847 "AnyThread": "0", 848 "EdgeDetect": "0", 849 "PEBS": "1", 850 "Offcore": "0" 851 }, 852 { 853 "EventCode": "0xF7", 854 "UMask": "0x4", 855 "EventName": "FP_ASSIST.INPUT", 856 "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", 857 "PublicDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", 858 "Counter": "0,1,2,3", 859 "SampleAfterValue": "20000", 860 "MSRIndex": "0", 861 "MSRValue": "0", 862 "CounterMask": "0", 863 "Invert": "0", 864 "AnyThread": "0", 865 "EdgeDetect": "0", 866 "PEBS": "1", 867 "Offcore": "0" 868 }, 869 { 870 "EventCode": "0xF7", 871 "UMask": "0x2", 872 "EventName": "FP_ASSIST.OUTPUT", 873 "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)", 874 "PublicDescription": "X87 Floating point assists for invalid output value (Precise Event)", 875 "Counter": "0,1,2,3", 876 "SampleAfterValue": "20000", 877 "MSRIndex": "0", 878 "MSRValue": "0", 879 "CounterMask": "0", 880 "Invert": "0", 881 "AnyThread": "0", 882 "EdgeDetect": "0", 883 "PEBS": "1", 884 "Offcore": "0" 885 }, 886 { 887 "EventCode": "0x10", 888 "UMask": "0x2", 889 "EventName": "FP_COMP_OPS_EXE.MMX", 890 "BriefDescription": "MMX Uops", 891 "PublicDescription": "MMX Uops", 892 "Counter": "0,1,2,3", 893 "SampleAfterValue": "2000000", 894 "MSRIndex": "0", 895 "MSRValue": "0", 896 "CounterMask": "0", 897 "Invert": "0", 898 "AnyThread": "0", 899 "EdgeDetect": "0", 900 "PEBS": "0", 901 "Offcore": "0" 902 }, 903 { 904 "EventCode": "0x10", 905 "UMask": "0x80", 906 "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", 907 "BriefDescription": "SSE* FP double precision Uops", 908 "PublicDescription": "SSE* FP double precision Uops", 909 "Counter": "0,1,2,3", 910 "SampleAfterValue": "2000000", 911 "MSRIndex": "0", 912 "MSRValue": "0", 913 "CounterMask": "0", 914 "Invert": "0", 915 "AnyThread": "0", 916 "EdgeDetect": "0", 917 "PEBS": "0", 918 "Offcore": "0" 919 }, 920 { 921 "EventCode": "0x10", 922 "UMask": "0x4", 923 "EventName": "FP_COMP_OPS_EXE.SSE_FP", 924 "BriefDescription": "SSE and SSE2 FP Uops", 925 "PublicDescription": "SSE and SSE2 FP Uops", 926 "Counter": "0,1,2,3", 927 "SampleAfterValue": "2000000", 928 "MSRIndex": "0", 929 "MSRValue": "0", 930 "CounterMask": "0", 931 "Invert": "0", 932 "AnyThread": "0", 933 "EdgeDetect": "0", 934 "PEBS": "0", 935 "Offcore": "0" 936 }, 937 { 938 "EventCode": "0x10", 939 "UMask": "0x10", 940 "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", 941 "BriefDescription": "SSE FP packed Uops", 942 "PublicDescription": "SSE FP packed Uops", 943 "Counter": "0,1,2,3", 944 "SampleAfterValue": "2000000", 945 "MSRIndex": "0", 946 "MSRValue": "0", 947 "CounterMask": "0", 948 "Invert": "0", 949 "AnyThread": "0", 950 "EdgeDetect": "0", 951 "PEBS": "0", 952 "Offcore": "0" 953 }, 954 { 955 "EventCode": "0x10", 956 "UMask": "0x20", 957 "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", 958 "BriefDescription": "SSE FP scalar Uops", 959 "PublicDescription": "SSE FP scalar Uops", 960 "Counter": "0,1,2,3", 961 "SampleAfterValue": "2000000", 962 "MSRIndex": "0", 963 "MSRValue": "0", 964 "CounterMask": "0", 965 "Invert": "0", 966 "AnyThread": "0", 967 "EdgeDetect": "0", 968 "PEBS": "0", 969 "Offcore": "0" 970 }, 971 { 972 "EventCode": "0x10", 973 "UMask": "0x40", 974 "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", 975 "BriefDescription": "SSE* FP single precision Uops", 976 "PublicDescription": "SSE* FP single precision Uops", 977 "Counter": "0,1,2,3", 978 "SampleAfterValue": "2000000", 979 "MSRIndex": "0", 980 "MSRValue": "0", 981 "CounterMask": "0", 982 "Invert": "0", 983 "AnyThread": "0", 984 "EdgeDetect": "0", 985 "PEBS": "0", 986 "Offcore": "0" 987 }, 988 { 989 "EventCode": "0x10", 990 "UMask": "0x8", 991 "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", 992 "BriefDescription": "SSE2 integer Uops", 993 "PublicDescription": "SSE2 integer Uops", 994 "Counter": "0,1,2,3", 995 "SampleAfterValue": "2000000", 996 "MSRIndex": "0", 997 "MSRValue": "0", 998 "CounterMask": "0", 999 "Invert": "0", 1000 "AnyThread": "0", 1001 "EdgeDetect": "0", 1002 "PEBS": "0", 1003 "Offcore": "0" 1004 }, 1005 { 1006 "EventCode": "0x10", 1007 "UMask": "0x1", 1008 "EventName": "FP_COMP_OPS_EXE.X87", 1009 "BriefDescription": "Computational floating-point operations executed", 1010 "PublicDescription": "Computational floating-point operations executed", 1011 "Counter": "0,1,2,3", 1012 "SampleAfterValue": "2000000", 1013 "MSRIndex": "0", 1014 "MSRValue": "0", 1015 "CounterMask": "0", 1016 "Invert": "0", 1017 "AnyThread": "0", 1018 "EdgeDetect": "0", 1019 "PEBS": "0", 1020 "Offcore": "0" 1021 }, 1022 { 1023 "EventCode": "0xCC", 1024 "UMask": "0x3", 1025 "EventName": "FP_MMX_TRANS.ANY", 1026 "BriefDescription": "All Floating Point to and from MMX transitions", 1027 "PublicDescription": "All Floating Point to and from MMX transitions", 1028 "Counter": "0,1,2,3", 1029 "SampleAfterValue": "2000000", 1030 "MSRIndex": "0", 1031 "MSRValue": "0", 1032 "CounterMask": "0", 1033 "Invert": "0", 1034 "AnyThread": "0", 1035 "EdgeDetect": "0", 1036 "PEBS": "0", 1037 "Offcore": "0" 1038 }, 1039 { 1040 "EventCode": "0xCC", 1041 "UMask": "0x1", 1042 "EventName": "FP_MMX_TRANS.TO_FP", 1043 "BriefDescription": "Transitions from MMX to Floating Point instructions", 1044 "PublicDescription": "Transitions from MMX to Floating Point instructions", 1045 "Counter": "0,1,2,3", 1046 "SampleAfterValue": "2000000", 1047 "MSRIndex": "0", 1048 "MSRValue": "0", 1049 "CounterMask": "0", 1050 "Invert": "0", 1051 "AnyThread": "0", 1052 "EdgeDetect": "0", 1053 "PEBS": "0", 1054 "Offcore": "0" 1055 }, 1056 { 1057 "EventCode": "0xCC", 1058 "UMask": "0x2", 1059 "EventName": "FP_MMX_TRANS.TO_MMX", 1060 "BriefDescription": "Transitions from Floating Point to MMX instructions", 1061 "PublicDescription": "Transitions from Floating Point to MMX instructions", 1062 "Counter": "0,1,2,3", 1063 "SampleAfterValue": "2000000", 1064 "MSRIndex": "0", 1065 "MSRValue": "0", 1066 "CounterMask": "0", 1067 "Invert": "0", 1068 "AnyThread": "0", 1069 "EdgeDetect": "0", 1070 "PEBS": "0", 1071 "Offcore": "0" 1072 }, 1073 { 1074 "EventCode": "0x87", 1075 "UMask": "0xF", 1076 "EventName": "ILD_STALL.ANY", 1077 "BriefDescription": "Any Instruction Length Decoder stall cycles", 1078 "PublicDescription": "Any Instruction Length Decoder stall cycles", 1079 "Counter": "0,1,2,3", 1080 "SampleAfterValue": "2000000", 1081 "MSRIndex": "0", 1082 "MSRValue": "0", 1083 "CounterMask": "0", 1084 "Invert": "0", 1085 "AnyThread": "0", 1086 "EdgeDetect": "0", 1087 "PEBS": "0", 1088 "Offcore": "0" 1089 }, 1090 { 1091 "EventCode": "0x87", 1092 "UMask": "0x4", 1093 "EventName": "ILD_STALL.IQ_FULL", 1094 "BriefDescription": "Instruction Queue full stall cycles", 1095 "PublicDescription": "Instruction Queue full stall cycles", 1096 "Counter": "0,1,2,3", 1097 "SampleAfterValue": "2000000", 1098 "MSRIndex": "0", 1099 "MSRValue": "0", 1100 "CounterMask": "0", 1101 "Invert": "0", 1102 "AnyThread": "0", 1103 "EdgeDetect": "0", 1104 "PEBS": "0", 1105 "Offcore": "0" 1106 }, 1107 { 1108 "EventCode": "0x87", 1109 "UMask": "0x1", 1110 "EventName": "ILD_STALL.LCP", 1111 "BriefDescription": "Length Change Prefix stall cycles", 1112 "PublicDescription": "Length Change Prefix stall cycles", 1113 "Counter": "0,1,2,3", 1114 "SampleAfterValue": "2000000", 1115 "MSRIndex": "0", 1116 "MSRValue": "0", 1117 "CounterMask": "0", 1118 "Invert": "0", 1119 "AnyThread": "0", 1120 "EdgeDetect": "0", 1121 "PEBS": "0", 1122 "Offcore": "0" 1123 }, 1124 { 1125 "EventCode": "0x87", 1126 "UMask": "0x2", 1127 "EventName": "ILD_STALL.MRU", 1128 "BriefDescription": "Stall cycles due to BPU MRU bypass", 1129 "PublicDescription": "Stall cycles due to BPU MRU bypass", 1130 "Counter": "0,1,2,3", 1131 "SampleAfterValue": "2000000", 1132 "MSRIndex": "0", 1133 "MSRValue": "0", 1134 "CounterMask": "0", 1135 "Invert": "0", 1136 "AnyThread": "0", 1137 "EdgeDetect": "0", 1138 "PEBS": "0", 1139 "Offcore": "0" 1140 }, 1141 { 1142 "EventCode": "0x87", 1143 "UMask": "0x8", 1144 "EventName": "ILD_STALL.REGEN", 1145 "BriefDescription": "Regen stall cycles", 1146 "PublicDescription": "Regen stall cycles", 1147 "Counter": "0,1,2,3", 1148 "SampleAfterValue": "2000000", 1149 "MSRIndex": "0", 1150 "MSRValue": "0", 1151 "CounterMask": "0", 1152 "Invert": "0", 1153 "AnyThread": "0", 1154 "EdgeDetect": "0", 1155 "PEBS": "0", 1156 "Offcore": "0" 1157 }, 1158 { 1159 "EventCode": "0x18", 1160 "UMask": "0x1", 1161 "EventName": "INST_DECODED.DEC0", 1162 "BriefDescription": "Instructions that must be decoded by decoder 0", 1163 "PublicDescription": "Instructions that must be decoded by decoder 0", 1164 "Counter": "0,1,2,3", 1165 "SampleAfterValue": "2000000", 1166 "MSRIndex": "0", 1167 "MSRValue": "0", 1168 "CounterMask": "0", 1169 "Invert": "0", 1170 "AnyThread": "0", 1171 "EdgeDetect": "0", 1172 "PEBS": "0", 1173 "Offcore": "0" 1174 }, 1175 { 1176 "EventCode": "0x1E", 1177 "UMask": "0x1", 1178 "EventName": "INST_QUEUE_WRITE_CYCLES", 1179 "BriefDescription": "Cycles instructions are written to the instruction queue", 1180 "PublicDescription": "Cycles instructions are written to the instruction queue", 1181 "Counter": "0,1,2,3", 1182 "SampleAfterValue": "2000000", 1183 "MSRIndex": "0", 1184 "MSRValue": "0", 1185 "CounterMask": "0", 1186 "Invert": "0", 1187 "AnyThread": "0", 1188 "EdgeDetect": "0", 1189 "PEBS": "0", 1190 "Offcore": "0" 1191 }, 1192 { 1193 "EventCode": "0x17", 1194 "UMask": "0x1", 1195 "EventName": "INST_QUEUE_WRITES", 1196 "BriefDescription": "Instructions written to instruction queue.", 1197 "PublicDescription": "Instructions written to instruction queue.", 1198 "Counter": "0,1,2,3", 1199 "SampleAfterValue": "2000000", 1200 "MSRIndex": "0", 1201 "MSRValue": "0", 1202 "CounterMask": "0", 1203 "Invert": "0", 1204 "AnyThread": "0", 1205 "EdgeDetect": "0", 1206 "PEBS": "0", 1207 "Offcore": "0" 1208 }, 1209 { 1210 "EventCode": "0x0", 1211 "UMask": "0x0", 1212 "EventName": "INST_RETIRED.ANY", 1213 "BriefDescription": "Instructions retired (fixed counter)", 1214 "PublicDescription": "Instructions retired (fixed counter)", 1215 "Counter": "Fixed counter 1", 1216 "SampleAfterValue": "2000000", 1217 "MSRIndex": "0", 1218 "MSRValue": "0", 1219 "CounterMask": "0", 1220 "Invert": "0", 1221 "AnyThread": "0", 1222 "EdgeDetect": "0", 1223 "PEBS": "0", 1224 "Offcore": "0" 1225 }, 1226 { 1227 "EventCode": "0xC0", 1228 "UMask": "0x1", 1229 "EventName": "INST_RETIRED.ANY_P", 1230 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", 1231 "PublicDescription": "Instructions retired (Programmable counter and Precise Event)", 1232 "Counter": "0,1,2,3", 1233 "SampleAfterValue": "2000000", 1234 "MSRIndex": "0", 1235 "MSRValue": "0", 1236 "CounterMask": "0", 1237 "Invert": "0", 1238 "AnyThread": "0", 1239 "EdgeDetect": "0", 1240 "PEBS": "1", 1241 "Offcore": "0" 1242 }, 1243 { 1244 "EventCode": "0xC0", 1245 "UMask": "0x4", 1246 "EventName": "INST_RETIRED.MMX", 1247 "BriefDescription": "Retired MMX instructions (Precise Event)", 1248 "PublicDescription": "Retired MMX instructions (Precise Event)", 1249 "Counter": "0,1,2,3", 1250 "SampleAfterValue": "2000000", 1251 "MSRIndex": "0", 1252 "MSRValue": "0", 1253 "CounterMask": "0", 1254 "Invert": "0", 1255 "AnyThread": "0", 1256 "EdgeDetect": "0", 1257 "PEBS": "1", 1258 "Offcore": "0" 1259 }, 1260 { 1261 "EventCode": "0xC0", 1262 "UMask": "0x1", 1263 "EventName": "INST_RETIRED.TOTAL_CYCLES", 1264 "BriefDescription": "Total cycles (Precise Event)", 1265 "PublicDescription": "Total cycles (Precise Event)", 1266 "Counter": "0,1,2,3", 1267 "SampleAfterValue": "2000000", 1268 "MSRIndex": "0", 1269 "MSRValue": "0", 1270 "CounterMask": "16", 1271 "Invert": "1", 1272 "AnyThread": "0", 1273 "EdgeDetect": "0", 1274 "PEBS": "1", 1275 "Offcore": "0" 1276 }, 1277 { 1278 "EventCode": "0xC0", 1279 "UMask": "0x2", 1280 "EventName": "INST_RETIRED.X87", 1281 "BriefDescription": "Retired floating-point operations (Precise Event)", 1282 "PublicDescription": "Retired floating-point operations (Precise Event)", 1283 "Counter": "0,1,2,3", 1284 "SampleAfterValue": "2000000", 1285 "MSRIndex": "0", 1286 "MSRValue": "0", 1287 "CounterMask": "0", 1288 "Invert": "0", 1289 "AnyThread": "0", 1290 "EdgeDetect": "0", 1291 "PEBS": "1", 1292 "Offcore": "0" 1293 }, 1294 { 1295 "EventCode": "0x6C", 1296 "UMask": "0x1", 1297 "EventName": "IO_TRANSACTIONS", 1298 "BriefDescription": "I/O transactions", 1299 "PublicDescription": "I/O transactions", 1300 "Counter": "0,1,2,3", 1301 "SampleAfterValue": "2000000", 1302 "MSRIndex": "0", 1303 "MSRValue": "0", 1304 "CounterMask": "0", 1305 "Invert": "0", 1306 "AnyThread": "0", 1307 "EdgeDetect": "0", 1308 "PEBS": "0", 1309 "Offcore": "0" 1310 }, 1311 { 1312 "EventCode": "0xAE", 1313 "UMask": "0x1", 1314 "EventName": "ITLB_FLUSH", 1315 "BriefDescription": "ITLB flushes", 1316 "PublicDescription": "ITLB flushes", 1317 "Counter": "0,1,2,3", 1318 "SampleAfterValue": "2000000", 1319 "MSRIndex": "0", 1320 "MSRValue": "0", 1321 "CounterMask": "0", 1322 "Invert": "0", 1323 "AnyThread": "0", 1324 "EdgeDetect": "0", 1325 "PEBS": "0", 1326 "Offcore": "0" 1327 }, 1328 { 1329 "EventCode": "0xC8", 1330 "UMask": "0x20", 1331 "EventName": "ITLB_MISS_RETIRED", 1332 "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", 1333 "PublicDescription": "Retired instructions that missed the ITLB (Precise Event)", 1334 "Counter": "0,1,2,3", 1335 "SampleAfterValue": "200000", 1336 "MSRIndex": "0", 1337 "MSRValue": "0", 1338 "CounterMask": "0", 1339 "Invert": "0", 1340 "AnyThread": "0", 1341 "EdgeDetect": "0", 1342 "PEBS": "1", 1343 "Offcore": "0" 1344 }, 1345 { 1346 "EventCode": "0x85", 1347 "UMask": "0x1", 1348 "EventName": "ITLB_MISSES.ANY", 1349 "BriefDescription": "ITLB miss", 1350 "PublicDescription": "ITLB miss", 1351 "Counter": "0,1,2,3", 1352 "SampleAfterValue": "200000", 1353 "MSRIndex": "0", 1354 "MSRValue": "0", 1355 "CounterMask": "0", 1356 "Invert": "0", 1357 "AnyThread": "0", 1358 "EdgeDetect": "0", 1359 "PEBS": "0", 1360 "Offcore": "0" 1361 }, 1362 { 1363 "EventCode": "0x85", 1364 "UMask": "0x2", 1365 "EventName": "ITLB_MISSES.WALK_COMPLETED", 1366 "BriefDescription": "ITLB miss page walks", 1367 "PublicDescription": "ITLB miss page walks", 1368 "Counter": "0,1,2,3", 1369 "SampleAfterValue": "200000", 1370 "MSRIndex": "0", 1371 "MSRValue": "0", 1372 "CounterMask": "0", 1373 "Invert": "0", 1374 "AnyThread": "0", 1375 "EdgeDetect": "0", 1376 "PEBS": "0", 1377 "Offcore": "0" 1378 }, 1379 { 1380 "EventCode": "0x51", 1381 "UMask": "0x4", 1382 "EventName": "L1D.M_EVICT", 1383 "BriefDescription": "L1D cache lines replaced in M state", 1384 "PublicDescription": "L1D cache lines replaced in M state", 1385 "Counter": "0,1", 1386 "SampleAfterValue": "2000000", 1387 "MSRIndex": "0", 1388 "MSRValue": "0", 1389 "CounterMask": "0", 1390 "Invert": "0", 1391 "AnyThread": "0", 1392 "EdgeDetect": "0", 1393 "PEBS": "0", 1394 "Offcore": "0" 1395 }, 1396 { 1397 "EventCode": "0x51", 1398 "UMask": "0x2", 1399 "EventName": "L1D.M_REPL", 1400 "BriefDescription": "L1D cache lines allocated in the M state", 1401 "PublicDescription": "L1D cache lines allocated in the M state", 1402 "Counter": "0,1", 1403 "SampleAfterValue": "2000000", 1404 "MSRIndex": "0", 1405 "MSRValue": "0", 1406 "CounterMask": "0", 1407 "Invert": "0", 1408 "AnyThread": "0", 1409 "EdgeDetect": "0", 1410 "PEBS": "0", 1411 "Offcore": "0" 1412 }, 1413 { 1414 "EventCode": "0x51", 1415 "UMask": "0x8", 1416 "EventName": "L1D.M_SNOOP_EVICT", 1417 "BriefDescription": "L1D snoop eviction of cache lines in M state", 1418 "PublicDescription": "L1D snoop eviction of cache lines in M state", 1419 "Counter": "0,1", 1420 "SampleAfterValue": "2000000", 1421 "MSRIndex": "0", 1422 "MSRValue": "0", 1423 "CounterMask": "0", 1424 "Invert": "0", 1425 "AnyThread": "0", 1426 "EdgeDetect": "0", 1427 "PEBS": "0", 1428 "Offcore": "0" 1429 }, 1430 { 1431 "EventCode": "0x51", 1432 "UMask": "0x1", 1433 "EventName": "L1D.REPL", 1434 "BriefDescription": "L1 data cache lines allocated", 1435 "PublicDescription": "L1 data cache lines allocated", 1436 "Counter": "0,1", 1437 "SampleAfterValue": "2000000", 1438 "MSRIndex": "0", 1439 "MSRValue": "0", 1440 "CounterMask": "0", 1441 "Invert": "0", 1442 "AnyThread": "0", 1443 "EdgeDetect": "0", 1444 "PEBS": "0", 1445 "Offcore": "0" 1446 }, 1447 { 1448 "EventCode": "0x43", 1449 "UMask": "0x1", 1450 "EventName": "L1D_ALL_REF.ANY", 1451 "BriefDescription": "All references to the L1 data cache", 1452 "PublicDescription": "All references to the L1 data cache", 1453 "Counter": "0,1", 1454 "SampleAfterValue": "2000000", 1455 "MSRIndex": "0", 1456 "MSRValue": "0", 1457 "CounterMask": "0", 1458 "Invert": "0", 1459 "AnyThread": "0", 1460 "EdgeDetect": "0", 1461 "PEBS": "0", 1462 "Offcore": "0" 1463 }, 1464 { 1465 "EventCode": "0x43", 1466 "UMask": "0x2", 1467 "EventName": "L1D_ALL_REF.CACHEABLE", 1468 "BriefDescription": "L1 data cacheable reads and writes", 1469 "PublicDescription": "L1 data cacheable reads and writes", 1470 "Counter": "0,1", 1471 "SampleAfterValue": "2000000", 1472 "MSRIndex": "0", 1473 "MSRValue": "0", 1474 "CounterMask": "0", 1475 "Invert": "0", 1476 "AnyThread": "0", 1477 "EdgeDetect": "0", 1478 "PEBS": "0", 1479 "Offcore": "0" 1480 }, 1481 { 1482 "EventCode": "0x40", 1483 "UMask": "0x4", 1484 "EventName": "L1D_CACHE_LD.E_STATE", 1485 "BriefDescription": "L1 data cache read in E state", 1486 "PublicDescription": "L1 data cache read in E state", 1487 "Counter": "0,1", 1488 "SampleAfterValue": "2000000", 1489 "MSRIndex": "0", 1490 "MSRValue": "0", 1491 "CounterMask": "0", 1492 "Invert": "0", 1493 "AnyThread": "0", 1494 "EdgeDetect": "0", 1495 "PEBS": "0", 1496 "Offcore": "0" 1497 }, 1498 { 1499 "EventCode": "0x40", 1500 "UMask": "0x1", 1501 "EventName": "L1D_CACHE_LD.I_STATE", 1502 "BriefDescription": "L1 data cache read in I state (misses)", 1503 "PublicDescription": "L1 data cache read in I state (misses)", 1504 "Counter": "0,1", 1505 "SampleAfterValue": "2000000", 1506 "MSRIndex": "0", 1507 "MSRValue": "0", 1508 "CounterMask": "0", 1509 "Invert": "0", 1510 "AnyThread": "0", 1511 "EdgeDetect": "0", 1512 "PEBS": "0", 1513 "Offcore": "0" 1514 }, 1515 { 1516 "EventCode": "0x40", 1517 "UMask": "0x8", 1518 "EventName": "L1D_CACHE_LD.M_STATE", 1519 "BriefDescription": "L1 data cache read in M state", 1520 "PublicDescription": "L1 data cache read in M state", 1521 "Counter": "0,1", 1522 "SampleAfterValue": "2000000", 1523 "MSRIndex": "0", 1524 "MSRValue": "0", 1525 "CounterMask": "0", 1526 "Invert": "0", 1527 "AnyThread": "0", 1528 "EdgeDetect": "0", 1529 "PEBS": "0", 1530 "Offcore": "0" 1531 }, 1532 { 1533 "EventCode": "0x40", 1534 "UMask": "0xF", 1535 "EventName": "L1D_CACHE_LD.MESI", 1536 "BriefDescription": "L1 data cache reads", 1537 "PublicDescription": "L1 data cache reads", 1538 "Counter": "0,1", 1539 "SampleAfterValue": "2000000", 1540 "MSRIndex": "0", 1541 "MSRValue": "0", 1542 "CounterMask": "0", 1543 "Invert": "0", 1544 "AnyThread": "0", 1545 "EdgeDetect": "0", 1546 "PEBS": "0", 1547 "Offcore": "0" 1548 }, 1549 { 1550 "EventCode": "0x40", 1551 "UMask": "0x2", 1552 "EventName": "L1D_CACHE_LD.S_STATE", 1553 "BriefDescription": "L1 data cache read in S state", 1554 "PublicDescription": "L1 data cache read in S state", 1555 "Counter": "0,1", 1556 "SampleAfterValue": "2000000", 1557 "MSRIndex": "0", 1558 "MSRValue": "0", 1559 "CounterMask": "0", 1560 "Invert": "0", 1561 "AnyThread": "0", 1562 "EdgeDetect": "0", 1563 "PEBS": "0", 1564 "Offcore": "0" 1565 }, 1566 { 1567 "EventCode": "0x42", 1568 "UMask": "0x4", 1569 "EventName": "L1D_CACHE_LOCK.E_STATE", 1570 "BriefDescription": "L1 data cache load locks in E state", 1571 "PublicDescription": "L1 data cache load locks in E state", 1572 "Counter": "0,1", 1573 "SampleAfterValue": "2000000", 1574 "MSRIndex": "0", 1575 "MSRValue": "0", 1576 "CounterMask": "0", 1577 "Invert": "0", 1578 "AnyThread": "0", 1579 "EdgeDetect": "0", 1580 "PEBS": "0", 1581 "Offcore": "0" 1582 }, 1583 { 1584 "EventCode": "0x42", 1585 "UMask": "0x1", 1586 "EventName": "L1D_CACHE_LOCK.HIT", 1587 "BriefDescription": "L1 data cache load lock hits", 1588 "PublicDescription": "L1 data cache load lock hits", 1589 "Counter": "0,1", 1590 "SampleAfterValue": "2000000", 1591 "MSRIndex": "0", 1592 "MSRValue": "0", 1593 "CounterMask": "0", 1594 "Invert": "0", 1595 "AnyThread": "0", 1596 "EdgeDetect": "0", 1597 "PEBS": "0", 1598 "Offcore": "0" 1599 }, 1600 { 1601 "EventCode": "0x42", 1602 "UMask": "0x8", 1603 "EventName": "L1D_CACHE_LOCK.M_STATE", 1604 "BriefDescription": "L1 data cache load locks in M state", 1605 "PublicDescription": "L1 data cache load locks in M state", 1606 "Counter": "0,1", 1607 "SampleAfterValue": "2000000", 1608 "MSRIndex": "0", 1609 "MSRValue": "0", 1610 "CounterMask": "0", 1611 "Invert": "0", 1612 "AnyThread": "0", 1613 "EdgeDetect": "0", 1614 "PEBS": "0", 1615 "Offcore": "0" 1616 }, 1617 { 1618 "EventCode": "0x42", 1619 "UMask": "0x2", 1620 "EventName": "L1D_CACHE_LOCK.S_STATE", 1621 "BriefDescription": "L1 data cache load locks in S state", 1622 "PublicDescription": "L1 data cache load locks in S state", 1623 "Counter": "0,1", 1624 "SampleAfterValue": "2000000", 1625 "MSRIndex": "0", 1626 "MSRValue": "0", 1627 "CounterMask": "0", 1628 "Invert": "0", 1629 "AnyThread": "0", 1630 "EdgeDetect": "0", 1631 "PEBS": "0", 1632 "Offcore": "0" 1633 }, 1634 { 1635 "EventCode": "0x53", 1636 "UMask": "0x1", 1637 "EventName": "L1D_CACHE_LOCK_FB_HIT", 1638 "BriefDescription": "L1D load lock accepted in fill buffer", 1639 "PublicDescription": "L1D load lock accepted in fill buffer", 1640 "Counter": "0,1", 1641 "SampleAfterValue": "2000000", 1642 "MSRIndex": "0", 1643 "MSRValue": "0", 1644 "CounterMask": "0", 1645 "Invert": "0", 1646 "AnyThread": "0", 1647 "EdgeDetect": "0", 1648 "PEBS": "0", 1649 "Offcore": "0" 1650 }, 1651 { 1652 "EventCode": "0x52", 1653 "UMask": "0x1", 1654 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 1655 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 1656 "PublicDescription": "L1D prefetch load lock accepted in fill buffer", 1657 "Counter": "0,1", 1658 "SampleAfterValue": "2000000", 1659 "MSRIndex": "0", 1660 "MSRValue": "0", 1661 "CounterMask": "0", 1662 "Invert": "0", 1663 "AnyThread": "0", 1664 "EdgeDetect": "0", 1665 "PEBS": "0", 1666 "Offcore": "0" 1667 }, 1668 { 1669 "EventCode": "0x41", 1670 "UMask": "0x4", 1671 "EventName": "L1D_CACHE_ST.E_STATE", 1672 "BriefDescription": "L1 data cache stores in E state", 1673 "PublicDescription": "L1 data cache stores in E state", 1674 "Counter": "0,1", 1675 "SampleAfterValue": "2000000", 1676 "MSRIndex": "0", 1677 "MSRValue": "0", 1678 "CounterMask": "0", 1679 "Invert": "0", 1680 "AnyThread": "0", 1681 "EdgeDetect": "0", 1682 "PEBS": "0", 1683 "Offcore": "0" 1684 }, 1685 { 1686 "EventCode": "0x41", 1687 "UMask": "0x8", 1688 "EventName": "L1D_CACHE_ST.M_STATE", 1689 "BriefDescription": "L1 data cache stores in M state", 1690 "PublicDescription": "L1 data cache stores in M state", 1691 "Counter": "0,1", 1692 "SampleAfterValue": "2000000", 1693 "MSRIndex": "0", 1694 "MSRValue": "0", 1695 "CounterMask": "0", 1696 "Invert": "0", 1697 "AnyThread": "0", 1698 "EdgeDetect": "0", 1699 "PEBS": "0", 1700 "Offcore": "0" 1701 }, 1702 { 1703 "EventCode": "0x41", 1704 "UMask": "0x2", 1705 "EventName": "L1D_CACHE_ST.S_STATE", 1706 "BriefDescription": "L1 data cache stores in S state", 1707 "PublicDescription": "L1 data cache stores in S state", 1708 "Counter": "0,1", 1709 "SampleAfterValue": "2000000", 1710 "MSRIndex": "0", 1711 "MSRValue": "0", 1712 "CounterMask": "0", 1713 "Invert": "0", 1714 "AnyThread": "0", 1715 "EdgeDetect": "0", 1716 "PEBS": "0", 1717 "Offcore": "0" 1718 }, 1719 { 1720 "EventCode": "0x4E", 1721 "UMask": "0x2", 1722 "EventName": "L1D_PREFETCH.MISS", 1723 "BriefDescription": "L1D hardware prefetch misses", 1724 "PublicDescription": "L1D hardware prefetch misses", 1725 "Counter": "0,1", 1726 "SampleAfterValue": "200000", 1727 "MSRIndex": "0", 1728 "MSRValue": "0", 1729 "CounterMask": "0", 1730 "Invert": "0", 1731 "AnyThread": "0", 1732 "EdgeDetect": "0", 1733 "PEBS": "0", 1734 "Offcore": "0" 1735 }, 1736 { 1737 "EventCode": "0x4E", 1738 "UMask": "0x1", 1739 "EventName": "L1D_PREFETCH.REQUESTS", 1740 "BriefDescription": "L1D hardware prefetch requests", 1741 "PublicDescription": "L1D hardware prefetch requests", 1742 "Counter": "0,1", 1743 "SampleAfterValue": "200000", 1744 "MSRIndex": "0", 1745 "MSRValue": "0", 1746 "CounterMask": "0", 1747 "Invert": "0", 1748 "AnyThread": "0", 1749 "EdgeDetect": "0", 1750 "PEBS": "0", 1751 "Offcore": "0" 1752 }, 1753 { 1754 "EventCode": "0x4E", 1755 "UMask": "0x4", 1756 "EventName": "L1D_PREFETCH.TRIGGERS", 1757 "BriefDescription": "L1D hardware prefetch requests triggered", 1758 "PublicDescription": "L1D hardware prefetch requests triggered", 1759 "Counter": "0,1", 1760 "SampleAfterValue": "200000", 1761 "MSRIndex": "0", 1762 "MSRValue": "0", 1763 "CounterMask": "0", 1764 "Invert": "0", 1765 "AnyThread": "0", 1766 "EdgeDetect": "0", 1767 "PEBS": "0", 1768 "Offcore": "0" 1769 }, 1770 { 1771 "EventCode": "0x28", 1772 "UMask": "0x4", 1773 "EventName": "L1D_WB_L2.E_STATE", 1774 "BriefDescription": "L1 writebacks to L2 in E state", 1775 "PublicDescription": "L1 writebacks to L2 in E state", 1776 "Counter": "0,1,2,3", 1777 "SampleAfterValue": "100000", 1778 "MSRIndex": "0", 1779 "MSRValue": "0", 1780 "CounterMask": "0", 1781 "Invert": "0", 1782 "AnyThread": "0", 1783 "EdgeDetect": "0", 1784 "PEBS": "0", 1785 "Offcore": "0" 1786 }, 1787 { 1788 "EventCode": "0x28", 1789 "UMask": "0x1", 1790 "EventName": "L1D_WB_L2.I_STATE", 1791 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 1792 "PublicDescription": "L1 writebacks to L2 in I state (misses)", 1793 "Counter": "0,1,2,3", 1794 "SampleAfterValue": "100000", 1795 "MSRIndex": "0", 1796 "MSRValue": "0", 1797 "CounterMask": "0", 1798 "Invert": "0", 1799 "AnyThread": "0", 1800 "EdgeDetect": "0", 1801 "PEBS": "0", 1802 "Offcore": "0" 1803 }, 1804 { 1805 "EventCode": "0x28", 1806 "UMask": "0x8", 1807 "EventName": "L1D_WB_L2.M_STATE", 1808 "BriefDescription": "L1 writebacks to L2 in M state", 1809 "PublicDescription": "L1 writebacks to L2 in M state", 1810 "Counter": "0,1,2,3", 1811 "SampleAfterValue": "100000", 1812 "MSRIndex": "0", 1813 "MSRValue": "0", 1814 "CounterMask": "0", 1815 "Invert": "0", 1816 "AnyThread": "0", 1817 "EdgeDetect": "0", 1818 "PEBS": "0", 1819 "Offcore": "0" 1820 }, 1821 { 1822 "EventCode": "0x28", 1823 "UMask": "0xF", 1824 "EventName": "L1D_WB_L2.MESI", 1825 "BriefDescription": "All L1 writebacks to L2", 1826 "PublicDescription": "All L1 writebacks to L2", 1827 "Counter": "0,1,2,3", 1828 "SampleAfterValue": "100000", 1829 "MSRIndex": "0", 1830 "MSRValue": "0", 1831 "CounterMask": "0", 1832 "Invert": "0", 1833 "AnyThread": "0", 1834 "EdgeDetect": "0", 1835 "PEBS": "0", 1836 "Offcore": "0" 1837 }, 1838 { 1839 "EventCode": "0x28", 1840 "UMask": "0x2", 1841 "EventName": "L1D_WB_L2.S_STATE", 1842 "BriefDescription": "L1 writebacks to L2 in S state", 1843 "PublicDescription": "L1 writebacks to L2 in S state", 1844 "Counter": "0,1,2,3", 1845 "SampleAfterValue": "100000", 1846 "MSRIndex": "0", 1847 "MSRValue": "0", 1848 "CounterMask": "0", 1849 "Invert": "0", 1850 "AnyThread": "0", 1851 "EdgeDetect": "0", 1852 "PEBS": "0", 1853 "Offcore": "0" 1854 }, 1855 { 1856 "EventCode": "0x80", 1857 "UMask": "0x4", 1858 "EventName": "L1I.CYCLES_STALLED", 1859 "BriefDescription": "L1I instruction fetch stall cycles", 1860 "PublicDescription": "L1I instruction fetch stall cycles", 1861 "Counter": "0,1,2,3", 1862 "SampleAfterValue": "2000000", 1863 "MSRIndex": "0", 1864 "MSRValue": "0", 1865 "CounterMask": "0", 1866 "Invert": "0", 1867 "AnyThread": "0", 1868 "EdgeDetect": "0", 1869 "PEBS": "0", 1870 "Offcore": "0" 1871 }, 1872 { 1873 "EventCode": "0x80", 1874 "UMask": "0x1", 1875 "EventName": "L1I.HITS", 1876 "BriefDescription": "L1I instruction fetch hits", 1877 "PublicDescription": "L1I instruction fetch hits", 1878 "Counter": "0,1,2,3", 1879 "SampleAfterValue": "2000000", 1880 "MSRIndex": "0", 1881 "MSRValue": "0", 1882 "CounterMask": "0", 1883 "Invert": "0", 1884 "AnyThread": "0", 1885 "EdgeDetect": "0", 1886 "PEBS": "0", 1887 "Offcore": "0" 1888 }, 1889 { 1890 "EventCode": "0x80", 1891 "UMask": "0x2", 1892 "EventName": "L1I.MISSES", 1893 "BriefDescription": "L1I instruction fetch misses", 1894 "PublicDescription": "L1I instruction fetch misses", 1895 "Counter": "0,1,2,3", 1896 "SampleAfterValue": "2000000", 1897 "MSRIndex": "0", 1898 "MSRValue": "0", 1899 "CounterMask": "0", 1900 "Invert": "0", 1901 "AnyThread": "0", 1902 "EdgeDetect": "0", 1903 "PEBS": "0", 1904 "Offcore": "0" 1905 }, 1906 { 1907 "EventCode": "0x80", 1908 "UMask": "0x3", 1909 "EventName": "L1I.READS", 1910 "BriefDescription": "L1I Instruction fetches", 1911 "PublicDescription": "L1I Instruction fetches", 1912 "Counter": "0,1,2,3", 1913 "SampleAfterValue": "2000000", 1914 "MSRIndex": "0", 1915 "MSRValue": "0", 1916 "CounterMask": "0", 1917 "Invert": "0", 1918 "AnyThread": "0", 1919 "EdgeDetect": "0", 1920 "PEBS": "0", 1921 "Offcore": "0" 1922 }, 1923 { 1924 "EventCode": "0x26", 1925 "UMask": "0xFF", 1926 "EventName": "L2_DATA_RQSTS.ANY", 1927 "BriefDescription": "All L2 data requests", 1928 "PublicDescription": "All L2 data requests", 1929 "Counter": "0,1,2,3", 1930 "SampleAfterValue": "200000", 1931 "MSRIndex": "0", 1932 "MSRValue": "0", 1933 "CounterMask": "0", 1934 "Invert": "0", 1935 "AnyThread": "0", 1936 "EdgeDetect": "0", 1937 "PEBS": "0", 1938 "Offcore": "0" 1939 }, 1940 { 1941 "EventCode": "0x26", 1942 "UMask": "0x4", 1943 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 1944 "BriefDescription": "L2 data demand loads in E state", 1945 "PublicDescription": "L2 data demand loads in E state", 1946 "Counter": "0,1,2,3", 1947 "SampleAfterValue": "200000", 1948 "MSRIndex": "0", 1949 "MSRValue": "0", 1950 "CounterMask": "0", 1951 "Invert": "0", 1952 "AnyThread": "0", 1953 "EdgeDetect": "0", 1954 "PEBS": "0", 1955 "Offcore": "0" 1956 }, 1957 { 1958 "EventCode": "0x26", 1959 "UMask": "0x1", 1960 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 1961 "BriefDescription": "L2 data demand loads in I state (misses)", 1962 "PublicDescription": "L2 data demand loads in I state (misses)", 1963 "Counter": "0,1,2,3", 1964 "SampleAfterValue": "200000", 1965 "MSRIndex": "0", 1966 "MSRValue": "0", 1967 "CounterMask": "0", 1968 "Invert": "0", 1969 "AnyThread": "0", 1970 "EdgeDetect": "0", 1971 "PEBS": "0", 1972 "Offcore": "0" 1973 }, 1974 { 1975 "EventCode": "0x26", 1976 "UMask": "0x8", 1977 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 1978 "BriefDescription": "L2 data demand loads in M state", 1979 "PublicDescription": "L2 data demand loads in M state", 1980 "Counter": "0,1,2,3", 1981 "SampleAfterValue": "200000", 1982 "MSRIndex": "0", 1983 "MSRValue": "0", 1984 "CounterMask": "0", 1985 "Invert": "0", 1986 "AnyThread": "0", 1987 "EdgeDetect": "0", 1988 "PEBS": "0", 1989 "Offcore": "0" 1990 }, 1991 { 1992 "EventCode": "0x26", 1993 "UMask": "0xF", 1994 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 1995 "BriefDescription": "L2 data demand requests", 1996 "PublicDescription": "L2 data demand requests", 1997 "Counter": "0,1,2,3", 1998 "SampleAfterValue": "200000", 1999 "MSRIndex": "0", 2000 "MSRValue": "0", 2001 "CounterMask": "0", 2002 "Invert": "0", 2003 "AnyThread": "0", 2004 "EdgeDetect": "0", 2005 "PEBS": "0", 2006 "Offcore": "0" 2007 }, 2008 { 2009 "EventCode": "0x26", 2010 "UMask": "0x2", 2011 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 2012 "BriefDescription": "L2 data demand loads in S state", 2013 "PublicDescription": "L2 data demand loads in S state", 2014 "Counter": "0,1,2,3", 2015 "SampleAfterValue": "200000", 2016 "MSRIndex": "0", 2017 "MSRValue": "0", 2018 "CounterMask": "0", 2019 "Invert": "0", 2020 "AnyThread": "0", 2021 "EdgeDetect": "0", 2022 "PEBS": "0", 2023 "Offcore": "0" 2024 }, 2025 { 2026 "EventCode": "0x26", 2027 "UMask": "0x40", 2028 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 2029 "BriefDescription": "L2 data prefetches in E state", 2030 "PublicDescription": "L2 data prefetches in E state", 2031 "Counter": "0,1,2,3", 2032 "SampleAfterValue": "200000", 2033 "MSRIndex": "0", 2034 "MSRValue": "0", 2035 "CounterMask": "0", 2036 "Invert": "0", 2037 "AnyThread": "0", 2038 "EdgeDetect": "0", 2039 "PEBS": "0", 2040 "Offcore": "0" 2041 }, 2042 { 2043 "EventCode": "0x26", 2044 "UMask": "0x10", 2045 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 2046 "BriefDescription": "L2 data prefetches in the I state (misses)", 2047 "PublicDescription": "L2 data prefetches in the I state (misses)", 2048 "Counter": "0,1,2,3", 2049 "SampleAfterValue": "200000", 2050 "MSRIndex": "0", 2051 "MSRValue": "0", 2052 "CounterMask": "0", 2053 "Invert": "0", 2054 "AnyThread": "0", 2055 "EdgeDetect": "0", 2056 "PEBS": "0", 2057 "Offcore": "0" 2058 }, 2059 { 2060 "EventCode": "0x26", 2061 "UMask": "0x80", 2062 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 2063 "BriefDescription": "L2 data prefetches in M state", 2064 "PublicDescription": "L2 data prefetches in M state", 2065 "Counter": "0,1,2,3", 2066 "SampleAfterValue": "200000", 2067 "MSRIndex": "0", 2068 "MSRValue": "0", 2069 "CounterMask": "0", 2070 "Invert": "0", 2071 "AnyThread": "0", 2072 "EdgeDetect": "0", 2073 "PEBS": "0", 2074 "Offcore": "0" 2075 }, 2076 { 2077 "EventCode": "0x26", 2078 "UMask": "0xF0", 2079 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 2080 "BriefDescription": "All L2 data prefetches", 2081 "PublicDescription": "All L2 data prefetches", 2082 "Counter": "0,1,2,3", 2083 "SampleAfterValue": "200000", 2084 "MSRIndex": "0", 2085 "MSRValue": "0", 2086 "CounterMask": "0", 2087 "Invert": "0", 2088 "AnyThread": "0", 2089 "EdgeDetect": "0", 2090 "PEBS": "0", 2091 "Offcore": "0" 2092 }, 2093 { 2094 "EventCode": "0x26", 2095 "UMask": "0x20", 2096 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 2097 "BriefDescription": "L2 data prefetches in the S state", 2098 "PublicDescription": "L2 data prefetches in the S state", 2099 "Counter": "0,1,2,3", 2100 "SampleAfterValue": "200000", 2101 "MSRIndex": "0", 2102 "MSRValue": "0", 2103 "CounterMask": "0", 2104 "Invert": "0", 2105 "AnyThread": "0", 2106 "EdgeDetect": "0", 2107 "PEBS": "0", 2108 "Offcore": "0" 2109 }, 2110 { 2111 "EventCode": "0xF1", 2112 "UMask": "0x7", 2113 "EventName": "L2_LINES_IN.ANY", 2114 "BriefDescription": "L2 lines alloacated", 2115 "PublicDescription": "L2 lines alloacated", 2116 "Counter": "0,1,2,3", 2117 "SampleAfterValue": "100000", 2118 "MSRIndex": "0", 2119 "MSRValue": "0", 2120 "CounterMask": "0", 2121 "Invert": "0", 2122 "AnyThread": "0", 2123 "EdgeDetect": "0", 2124 "PEBS": "0", 2125 "Offcore": "0" 2126 }, 2127 { 2128 "EventCode": "0xF1", 2129 "UMask": "0x4", 2130 "EventName": "L2_LINES_IN.E_STATE", 2131 "BriefDescription": "L2 lines allocated in the E state", 2132 "PublicDescription": "L2 lines allocated in the E state", 2133 "Counter": "0,1,2,3", 2134 "SampleAfterValue": "100000", 2135 "MSRIndex": "0", 2136 "MSRValue": "0", 2137 "CounterMask": "0", 2138 "Invert": "0", 2139 "AnyThread": "0", 2140 "EdgeDetect": "0", 2141 "PEBS": "0", 2142 "Offcore": "0" 2143 }, 2144 { 2145 "EventCode": "0xF1", 2146 "UMask": "0x2", 2147 "EventName": "L2_LINES_IN.S_STATE", 2148 "BriefDescription": "L2 lines allocated in the S state", 2149 "PublicDescription": "L2 lines allocated in the S state", 2150 "Counter": "0,1,2,3", 2151 "SampleAfterValue": "100000", 2152 "MSRIndex": "0", 2153 "MSRValue": "0", 2154 "CounterMask": "0", 2155 "Invert": "0", 2156 "AnyThread": "0", 2157 "EdgeDetect": "0", 2158 "PEBS": "0", 2159 "Offcore": "0" 2160 }, 2161 { 2162 "EventCode": "0xF2", 2163 "UMask": "0xF", 2164 "EventName": "L2_LINES_OUT.ANY", 2165 "BriefDescription": "L2 lines evicted", 2166 "PublicDescription": "L2 lines evicted", 2167 "Counter": "0,1,2,3", 2168 "SampleAfterValue": "100000", 2169 "MSRIndex": "0", 2170 "MSRValue": "0", 2171 "CounterMask": "0", 2172 "Invert": "0", 2173 "AnyThread": "0", 2174 "EdgeDetect": "0", 2175 "PEBS": "0", 2176 "Offcore": "0" 2177 }, 2178 { 2179 "EventCode": "0xF2", 2180 "UMask": "0x1", 2181 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 2182 "BriefDescription": "L2 lines evicted by a demand request", 2183 "PublicDescription": "L2 lines evicted by a demand request", 2184 "Counter": "0,1,2,3", 2185 "SampleAfterValue": "100000", 2186 "MSRIndex": "0", 2187 "MSRValue": "0", 2188 "CounterMask": "0", 2189 "Invert": "0", 2190 "AnyThread": "0", 2191 "EdgeDetect": "0", 2192 "PEBS": "0", 2193 "Offcore": "0" 2194 }, 2195 { 2196 "EventCode": "0xF2", 2197 "UMask": "0x2", 2198 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 2199 "BriefDescription": "L2 modified lines evicted by a demand request", 2200 "PublicDescription": "L2 modified lines evicted by a demand request", 2201 "Counter": "0,1,2,3", 2202 "SampleAfterValue": "100000", 2203 "MSRIndex": "0", 2204 "MSRValue": "0", 2205 "CounterMask": "0", 2206 "Invert": "0", 2207 "AnyThread": "0", 2208 "EdgeDetect": "0", 2209 "PEBS": "0", 2210 "Offcore": "0" 2211 }, 2212 { 2213 "EventCode": "0xF2", 2214 "UMask": "0x4", 2215 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 2216 "BriefDescription": "L2 lines evicted by a prefetch request", 2217 "PublicDescription": "L2 lines evicted by a prefetch request", 2218 "Counter": "0,1,2,3", 2219 "SampleAfterValue": "100000", 2220 "MSRIndex": "0", 2221 "MSRValue": "0", 2222 "CounterMask": "0", 2223 "Invert": "0", 2224 "AnyThread": "0", 2225 "EdgeDetect": "0", 2226 "PEBS": "0", 2227 "Offcore": "0" 2228 }, 2229 { 2230 "EventCode": "0xF2", 2231 "UMask": "0x8", 2232 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 2233 "BriefDescription": "L2 modified lines evicted by a prefetch request", 2234 "PublicDescription": "L2 modified lines evicted by a prefetch request", 2235 "Counter": "0,1,2,3", 2236 "SampleAfterValue": "100000", 2237 "MSRIndex": "0", 2238 "MSRValue": "0", 2239 "CounterMask": "0", 2240 "Invert": "0", 2241 "AnyThread": "0", 2242 "EdgeDetect": "0", 2243 "PEBS": "0", 2244 "Offcore": "0" 2245 }, 2246 { 2247 "EventCode": "0x24", 2248 "UMask": "0x10", 2249 "EventName": "L2_RQSTS.IFETCH_HIT", 2250 "BriefDescription": "L2 instruction fetch hits", 2251 "PublicDescription": "L2 instruction fetch hits", 2252 "Counter": "0,1,2,3", 2253 "SampleAfterValue": "200000", 2254 "MSRIndex": "0", 2255 "MSRValue": "0", 2256 "CounterMask": "0", 2257 "Invert": "0", 2258 "AnyThread": "0", 2259 "EdgeDetect": "0", 2260 "PEBS": "0", 2261 "Offcore": "0" 2262 }, 2263 { 2264 "EventCode": "0x24", 2265 "UMask": "0x20", 2266 "EventName": "L2_RQSTS.IFETCH_MISS", 2267 "BriefDescription": "L2 instruction fetch misses", 2268 "PublicDescription": "L2 instruction fetch misses", 2269 "Counter": "0,1,2,3", 2270 "SampleAfterValue": "200000", 2271 "MSRIndex": "0", 2272 "MSRValue": "0", 2273 "CounterMask": "0", 2274 "Invert": "0", 2275 "AnyThread": "0", 2276 "EdgeDetect": "0", 2277 "PEBS": "0", 2278 "Offcore": "0" 2279 }, 2280 { 2281 "EventCode": "0x24", 2282 "UMask": "0x30", 2283 "EventName": "L2_RQSTS.IFETCHES", 2284 "BriefDescription": "L2 instruction fetches", 2285 "PublicDescription": "L2 instruction fetches", 2286 "Counter": "0,1,2,3", 2287 "SampleAfterValue": "200000", 2288 "MSRIndex": "0", 2289 "MSRValue": "0", 2290 "CounterMask": "0", 2291 "Invert": "0", 2292 "AnyThread": "0", 2293 "EdgeDetect": "0", 2294 "PEBS": "0", 2295 "Offcore": "0" 2296 }, 2297 { 2298 "EventCode": "0x24", 2299 "UMask": "0x1", 2300 "EventName": "L2_RQSTS.LD_HIT", 2301 "BriefDescription": "L2 load hits", 2302 "PublicDescription": "L2 load hits", 2303 "Counter": "0,1,2,3", 2304 "SampleAfterValue": "200000", 2305 "MSRIndex": "0", 2306 "MSRValue": "0", 2307 "CounterMask": "0", 2308 "Invert": "0", 2309 "AnyThread": "0", 2310 "EdgeDetect": "0", 2311 "PEBS": "0", 2312 "Offcore": "0" 2313 }, 2314 { 2315 "EventCode": "0x24", 2316 "UMask": "0x2", 2317 "EventName": "L2_RQSTS.LD_MISS", 2318 "BriefDescription": "L2 load misses", 2319 "PublicDescription": "L2 load misses", 2320 "Counter": "0,1,2,3", 2321 "SampleAfterValue": "200000", 2322 "MSRIndex": "0", 2323 "MSRValue": "0", 2324 "CounterMask": "0", 2325 "Invert": "0", 2326 "AnyThread": "0", 2327 "EdgeDetect": "0", 2328 "PEBS": "0", 2329 "Offcore": "0" 2330 }, 2331 { 2332 "EventCode": "0x24", 2333 "UMask": "0x3", 2334 "EventName": "L2_RQSTS.LOADS", 2335 "BriefDescription": "L2 requests", 2336 "PublicDescription": "L2 requests", 2337 "Counter": "0,1,2,3", 2338 "SampleAfterValue": "200000", 2339 "MSRIndex": "0", 2340 "MSRValue": "0", 2341 "CounterMask": "0", 2342 "Invert": "0", 2343 "AnyThread": "0", 2344 "EdgeDetect": "0", 2345 "PEBS": "0", 2346 "Offcore": "0" 2347 }, 2348 { 2349 "EventCode": "0x24", 2350 "UMask": "0xAA", 2351 "EventName": "L2_RQSTS.MISS", 2352 "BriefDescription": "All L2 misses", 2353 "PublicDescription": "All L2 misses", 2354 "Counter": "0,1,2,3", 2355 "SampleAfterValue": "200000", 2356 "MSRIndex": "0", 2357 "MSRValue": "0", 2358 "CounterMask": "0", 2359 "Invert": "0", 2360 "AnyThread": "0", 2361 "EdgeDetect": "0", 2362 "PEBS": "0", 2363 "Offcore": "0" 2364 }, 2365 { 2366 "EventCode": "0x24", 2367 "UMask": "0x40", 2368 "EventName": "L2_RQSTS.PREFETCH_HIT", 2369 "BriefDescription": "L2 prefetch hits", 2370 "PublicDescription": "L2 prefetch hits", 2371 "Counter": "0,1,2,3", 2372 "SampleAfterValue": "200000", 2373 "MSRIndex": "0", 2374 "MSRValue": "0", 2375 "CounterMask": "0", 2376 "Invert": "0", 2377 "AnyThread": "0", 2378 "EdgeDetect": "0", 2379 "PEBS": "0", 2380 "Offcore": "0" 2381 }, 2382 { 2383 "EventCode": "0x24", 2384 "UMask": "0x80", 2385 "EventName": "L2_RQSTS.PREFETCH_MISS", 2386 "BriefDescription": "L2 prefetch misses", 2387 "PublicDescription": "L2 prefetch misses", 2388 "Counter": "0,1,2,3", 2389 "SampleAfterValue": "200000", 2390 "MSRIndex": "0", 2391 "MSRValue": "0", 2392 "CounterMask": "0", 2393 "Invert": "0", 2394 "AnyThread": "0", 2395 "EdgeDetect": "0", 2396 "PEBS": "0", 2397 "Offcore": "0" 2398 }, 2399 { 2400 "EventCode": "0x24", 2401 "UMask": "0xC0", 2402 "EventName": "L2_RQSTS.PREFETCHES", 2403 "BriefDescription": "All L2 prefetches", 2404 "PublicDescription": "All L2 prefetches", 2405 "Counter": "0,1,2,3", 2406 "SampleAfterValue": "200000", 2407 "MSRIndex": "0", 2408 "MSRValue": "0", 2409 "CounterMask": "0", 2410 "Invert": "0", 2411 "AnyThread": "0", 2412 "EdgeDetect": "0", 2413 "PEBS": "0", 2414 "Offcore": "0" 2415 }, 2416 { 2417 "EventCode": "0x24", 2418 "UMask": "0xFF", 2419 "EventName": "L2_RQSTS.REFERENCES", 2420 "BriefDescription": "All L2 requests", 2421 "PublicDescription": "All L2 requests", 2422 "Counter": "0,1,2,3", 2423 "SampleAfterValue": "200000", 2424 "MSRIndex": "0", 2425 "MSRValue": "0", 2426 "CounterMask": "0", 2427 "Invert": "0", 2428 "AnyThread": "0", 2429 "EdgeDetect": "0", 2430 "PEBS": "0", 2431 "Offcore": "0" 2432 }, 2433 { 2434 "EventCode": "0x24", 2435 "UMask": "0x4", 2436 "EventName": "L2_RQSTS.RFO_HIT", 2437 "BriefDescription": "L2 RFO hits", 2438 "PublicDescription": "L2 RFO hits", 2439 "Counter": "0,1,2,3", 2440 "SampleAfterValue": "200000", 2441 "MSRIndex": "0", 2442 "MSRValue": "0", 2443 "CounterMask": "0", 2444 "Invert": "0", 2445 "AnyThread": "0", 2446 "EdgeDetect": "0", 2447 "PEBS": "0", 2448 "Offcore": "0" 2449 }, 2450 { 2451 "EventCode": "0x24", 2452 "UMask": "0x8", 2453 "EventName": "L2_RQSTS.RFO_MISS", 2454 "BriefDescription": "L2 RFO misses", 2455 "PublicDescription": "L2 RFO misses", 2456 "Counter": "0,1,2,3", 2457 "SampleAfterValue": "200000", 2458 "MSRIndex": "0", 2459 "MSRValue": "0", 2460 "CounterMask": "0", 2461 "Invert": "0", 2462 "AnyThread": "0", 2463 "EdgeDetect": "0", 2464 "PEBS": "0", 2465 "Offcore": "0" 2466 }, 2467 { 2468 "EventCode": "0x24", 2469 "UMask": "0xC", 2470 "EventName": "L2_RQSTS.RFOS", 2471 "BriefDescription": "L2 RFO requests", 2472 "PublicDescription": "L2 RFO requests", 2473 "Counter": "0,1,2,3", 2474 "SampleAfterValue": "200000", 2475 "MSRIndex": "0", 2476 "MSRValue": "0", 2477 "CounterMask": "0", 2478 "Invert": "0", 2479 "AnyThread": "0", 2480 "EdgeDetect": "0", 2481 "PEBS": "0", 2482 "Offcore": "0" 2483 }, 2484 { 2485 "EventCode": "0xF0", 2486 "UMask": "0x80", 2487 "EventName": "L2_TRANSACTIONS.ANY", 2488 "BriefDescription": "All L2 transactions", 2489 "PublicDescription": "All L2 transactions", 2490 "Counter": "0,1,2,3", 2491 "SampleAfterValue": "200000", 2492 "MSRIndex": "0", 2493 "MSRValue": "0", 2494 "CounterMask": "0", 2495 "Invert": "0", 2496 "AnyThread": "0", 2497 "EdgeDetect": "0", 2498 "PEBS": "0", 2499 "Offcore": "0" 2500 }, 2501 { 2502 "EventCode": "0xF0", 2503 "UMask": "0x20", 2504 "EventName": "L2_TRANSACTIONS.FILL", 2505 "BriefDescription": "L2 fill transactions", 2506 "PublicDescription": "L2 fill transactions", 2507 "Counter": "0,1,2,3", 2508 "SampleAfterValue": "200000", 2509 "MSRIndex": "0", 2510 "MSRValue": "0", 2511 "CounterMask": "0", 2512 "Invert": "0", 2513 "AnyThread": "0", 2514 "EdgeDetect": "0", 2515 "PEBS": "0", 2516 "Offcore": "0" 2517 }, 2518 { 2519 "EventCode": "0xF0", 2520 "UMask": "0x4", 2521 "EventName": "L2_TRANSACTIONS.IFETCH", 2522 "BriefDescription": "L2 instruction fetch transactions", 2523 "PublicDescription": "L2 instruction fetch transactions", 2524 "Counter": "0,1,2,3", 2525 "SampleAfterValue": "200000", 2526 "MSRIndex": "0", 2527 "MSRValue": "0", 2528 "CounterMask": "0", 2529 "Invert": "0", 2530 "AnyThread": "0", 2531 "EdgeDetect": "0", 2532 "PEBS": "0", 2533 "Offcore": "0" 2534 }, 2535 { 2536 "EventCode": "0xF0", 2537 "UMask": "0x10", 2538 "EventName": "L2_TRANSACTIONS.L1D_WB", 2539 "BriefDescription": "L1D writeback to L2 transactions", 2540 "PublicDescription": "L1D writeback to L2 transactions", 2541 "Counter": "0,1,2,3", 2542 "SampleAfterValue": "200000", 2543 "MSRIndex": "0", 2544 "MSRValue": "0", 2545 "CounterMask": "0", 2546 "Invert": "0", 2547 "AnyThread": "0", 2548 "EdgeDetect": "0", 2549 "PEBS": "0", 2550 "Offcore": "0" 2551 }, 2552 { 2553 "EventCode": "0xF0", 2554 "UMask": "0x1", 2555 "EventName": "L2_TRANSACTIONS.LOAD", 2556 "BriefDescription": "L2 Load transactions", 2557 "PublicDescription": "L2 Load transactions", 2558 "Counter": "0,1,2,3", 2559 "SampleAfterValue": "200000", 2560 "MSRIndex": "0", 2561 "MSRValue": "0", 2562 "CounterMask": "0", 2563 "Invert": "0", 2564 "AnyThread": "0", 2565 "EdgeDetect": "0", 2566 "PEBS": "0", 2567 "Offcore": "0" 2568 }, 2569 { 2570 "EventCode": "0xF0", 2571 "UMask": "0x8", 2572 "EventName": "L2_TRANSACTIONS.PREFETCH", 2573 "BriefDescription": "L2 prefetch transactions", 2574 "PublicDescription": "L2 prefetch transactions", 2575 "Counter": "0,1,2,3", 2576 "SampleAfterValue": "200000", 2577 "MSRIndex": "0", 2578 "MSRValue": "0", 2579 "CounterMask": "0", 2580 "Invert": "0", 2581 "AnyThread": "0", 2582 "EdgeDetect": "0", 2583 "PEBS": "0", 2584 "Offcore": "0" 2585 }, 2586 { 2587 "EventCode": "0xF0", 2588 "UMask": "0x2", 2589 "EventName": "L2_TRANSACTIONS.RFO", 2590 "BriefDescription": "L2 RFO transactions", 2591 "PublicDescription": "L2 RFO transactions", 2592 "Counter": "0,1,2,3", 2593 "SampleAfterValue": "200000", 2594 "MSRIndex": "0", 2595 "MSRValue": "0", 2596 "CounterMask": "0", 2597 "Invert": "0", 2598 "AnyThread": "0", 2599 "EdgeDetect": "0", 2600 "PEBS": "0", 2601 "Offcore": "0" 2602 }, 2603 { 2604 "EventCode": "0xF0", 2605 "UMask": "0x40", 2606 "EventName": "L2_TRANSACTIONS.WB", 2607 "BriefDescription": "L2 writeback to LLC transactions", 2608 "PublicDescription": "L2 writeback to LLC transactions", 2609 "Counter": "0,1,2,3", 2610 "SampleAfterValue": "200000", 2611 "MSRIndex": "0", 2612 "MSRValue": "0", 2613 "CounterMask": "0", 2614 "Invert": "0", 2615 "AnyThread": "0", 2616 "EdgeDetect": "0", 2617 "PEBS": "0", 2618 "Offcore": "0" 2619 }, 2620 { 2621 "EventCode": "0x27", 2622 "UMask": "0x40", 2623 "EventName": "L2_WRITE.LOCK.E_STATE", 2624 "BriefDescription": "L2 demand lock RFOs in E state", 2625 "PublicDescription": "L2 demand lock RFOs in E state", 2626 "Counter": "0,1,2,3", 2627 "SampleAfterValue": "100000", 2628 "MSRIndex": "0", 2629 "MSRValue": "0", 2630 "CounterMask": "0", 2631 "Invert": "0", 2632 "AnyThread": "0", 2633 "EdgeDetect": "0", 2634 "PEBS": "0", 2635 "Offcore": "0" 2636 }, 2637 { 2638 "EventCode": "0x27", 2639 "UMask": "0xE0", 2640 "EventName": "L2_WRITE.LOCK.HIT", 2641 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 2642 "PublicDescription": "All demand L2 lock RFOs that hit the cache", 2643 "Counter": "0,1,2,3", 2644 "SampleAfterValue": "100000", 2645 "MSRIndex": "0", 2646 "MSRValue": "0", 2647 "CounterMask": "0", 2648 "Invert": "0", 2649 "AnyThread": "0", 2650 "EdgeDetect": "0", 2651 "PEBS": "0", 2652 "Offcore": "0" 2653 }, 2654 { 2655 "EventCode": "0x27", 2656 "UMask": "0x10", 2657 "EventName": "L2_WRITE.LOCK.I_STATE", 2658 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 2659 "PublicDescription": "L2 demand lock RFOs in I state (misses)", 2660 "Counter": "0,1,2,3", 2661 "SampleAfterValue": "100000", 2662 "MSRIndex": "0", 2663 "MSRValue": "0", 2664 "CounterMask": "0", 2665 "Invert": "0", 2666 "AnyThread": "0", 2667 "EdgeDetect": "0", 2668 "PEBS": "0", 2669 "Offcore": "0" 2670 }, 2671 { 2672 "EventCode": "0x27", 2673 "UMask": "0x80", 2674 "EventName": "L2_WRITE.LOCK.M_STATE", 2675 "BriefDescription": "L2 demand lock RFOs in M state", 2676 "PublicDescription": "L2 demand lock RFOs in M state", 2677 "Counter": "0,1,2,3", 2678 "SampleAfterValue": "100000", 2679 "MSRIndex": "0", 2680 "MSRValue": "0", 2681 "CounterMask": "0", 2682 "Invert": "0", 2683 "AnyThread": "0", 2684 "EdgeDetect": "0", 2685 "PEBS": "0", 2686 "Offcore": "0" 2687 }, 2688 { 2689 "EventCode": "0x27", 2690 "UMask": "0xF0", 2691 "EventName": "L2_WRITE.LOCK.MESI", 2692 "BriefDescription": "All demand L2 lock RFOs", 2693 "PublicDescription": "All demand L2 lock RFOs", 2694 "Counter": "0,1,2,3", 2695 "SampleAfterValue": "100000", 2696 "MSRIndex": "0", 2697 "MSRValue": "0", 2698 "CounterMask": "0", 2699 "Invert": "0", 2700 "AnyThread": "0", 2701 "EdgeDetect": "0", 2702 "PEBS": "0", 2703 "Offcore": "0" 2704 }, 2705 { 2706 "EventCode": "0x27", 2707 "UMask": "0x20", 2708 "EventName": "L2_WRITE.LOCK.S_STATE", 2709 "BriefDescription": "L2 demand lock RFOs in S state", 2710 "PublicDescription": "L2 demand lock RFOs in S state", 2711 "Counter": "0,1,2,3", 2712 "SampleAfterValue": "100000", 2713 "MSRIndex": "0", 2714 "MSRValue": "0", 2715 "CounterMask": "0", 2716 "Invert": "0", 2717 "AnyThread": "0", 2718 "EdgeDetect": "0", 2719 "PEBS": "0", 2720 "Offcore": "0" 2721 }, 2722 { 2723 "EventCode": "0x27", 2724 "UMask": "0xE", 2725 "EventName": "L2_WRITE.RFO.HIT", 2726 "BriefDescription": "All L2 demand store RFOs that hit the cache", 2727 "PublicDescription": "All L2 demand store RFOs that hit the cache", 2728 "Counter": "0,1,2,3", 2729 "SampleAfterValue": "100000", 2730 "MSRIndex": "0", 2731 "MSRValue": "0", 2732 "CounterMask": "0", 2733 "Invert": "0", 2734 "AnyThread": "0", 2735 "EdgeDetect": "0", 2736 "PEBS": "0", 2737 "Offcore": "0" 2738 }, 2739 { 2740 "EventCode": "0x27", 2741 "UMask": "0x1", 2742 "EventName": "L2_WRITE.RFO.I_STATE", 2743 "BriefDescription": "L2 demand store RFOs in I state (misses)", 2744 "PublicDescription": "L2 demand store RFOs in I state (misses)", 2745 "Counter": "0,1,2,3", 2746 "SampleAfterValue": "100000", 2747 "MSRIndex": "0", 2748 "MSRValue": "0", 2749 "CounterMask": "0", 2750 "Invert": "0", 2751 "AnyThread": "0", 2752 "EdgeDetect": "0", 2753 "PEBS": "0", 2754 "Offcore": "0" 2755 }, 2756 { 2757 "EventCode": "0x27", 2758 "UMask": "0x8", 2759 "EventName": "L2_WRITE.RFO.M_STATE", 2760 "BriefDescription": "L2 demand store RFOs in M state", 2761 "PublicDescription": "L2 demand store RFOs in M state", 2762 "Counter": "0,1,2,3", 2763 "SampleAfterValue": "100000", 2764 "MSRIndex": "0", 2765 "MSRValue": "0", 2766 "CounterMask": "0", 2767 "Invert": "0", 2768 "AnyThread": "0", 2769 "EdgeDetect": "0", 2770 "PEBS": "0", 2771 "Offcore": "0" 2772 }, 2773 { 2774 "EventCode": "0x27", 2775 "UMask": "0xF", 2776 "EventName": "L2_WRITE.RFO.MESI", 2777 "BriefDescription": "All L2 demand store RFOs", 2778 "PublicDescription": "All L2 demand store RFOs", 2779 "Counter": "0,1,2,3", 2780 "SampleAfterValue": "100000", 2781 "MSRIndex": "0", 2782 "MSRValue": "0", 2783 "CounterMask": "0", 2784 "Invert": "0", 2785 "AnyThread": "0", 2786 "EdgeDetect": "0", 2787 "PEBS": "0", 2788 "Offcore": "0" 2789 }, 2790 { 2791 "EventCode": "0x27", 2792 "UMask": "0x2", 2793 "EventName": "L2_WRITE.RFO.S_STATE", 2794 "BriefDescription": "L2 demand store RFOs in S state", 2795 "PublicDescription": "L2 demand store RFOs in S state", 2796 "Counter": "0,1,2,3", 2797 "SampleAfterValue": "100000", 2798 "MSRIndex": "0", 2799 "MSRValue": "0", 2800 "CounterMask": "0", 2801 "Invert": "0", 2802 "AnyThread": "0", 2803 "EdgeDetect": "0", 2804 "PEBS": "0", 2805 "Offcore": "0" 2806 }, 2807 { 2808 "EventCode": "0x82", 2809 "UMask": "0x1", 2810 "EventName": "LARGE_ITLB.HIT", 2811 "BriefDescription": "Large ITLB hit", 2812 "PublicDescription": "Large ITLB hit", 2813 "Counter": "0,1,2,3", 2814 "SampleAfterValue": "200000", 2815 "MSRIndex": "0", 2816 "MSRValue": "0", 2817 "CounterMask": "0", 2818 "Invert": "0", 2819 "AnyThread": "0", 2820 "EdgeDetect": "0", 2821 "PEBS": "0", 2822 "Offcore": "0" 2823 }, 2824 { 2825 "EventCode": "0x13", 2826 "UMask": "0x7", 2827 "EventName": "LOAD_DISPATCH.ANY", 2828 "BriefDescription": "All loads dispatched", 2829 "PublicDescription": "All loads dispatched", 2830 "Counter": "0,1,2,3", 2831 "SampleAfterValue": "2000000", 2832 "MSRIndex": "0", 2833 "MSRValue": "0", 2834 "CounterMask": "0", 2835 "Invert": "0", 2836 "AnyThread": "0", 2837 "EdgeDetect": "0", 2838 "PEBS": "0", 2839 "Offcore": "0" 2840 }, 2841 { 2842 "EventCode": "0x13", 2843 "UMask": "0x4", 2844 "EventName": "LOAD_DISPATCH.MOB", 2845 "BriefDescription": "Loads dispatched from the MOB", 2846 "PublicDescription": "Loads dispatched from the MOB", 2847 "Counter": "0,1,2,3", 2848 "SampleAfterValue": "2000000", 2849 "MSRIndex": "0", 2850 "MSRValue": "0", 2851 "CounterMask": "0", 2852 "Invert": "0", 2853 "AnyThread": "0", 2854 "EdgeDetect": "0", 2855 "PEBS": "0", 2856 "Offcore": "0" 2857 }, 2858 { 2859 "EventCode": "0x13", 2860 "UMask": "0x1", 2861 "EventName": "LOAD_DISPATCH.RS", 2862 "BriefDescription": "Loads dispatched that bypass the MOB", 2863 "PublicDescription": "Loads dispatched that bypass the MOB", 2864 "Counter": "0,1,2,3", 2865 "SampleAfterValue": "2000000", 2866 "MSRIndex": "0", 2867 "MSRValue": "0", 2868 "CounterMask": "0", 2869 "Invert": "0", 2870 "AnyThread": "0", 2871 "EdgeDetect": "0", 2872 "PEBS": "0", 2873 "Offcore": "0" 2874 }, 2875 { 2876 "EventCode": "0x13", 2877 "UMask": "0x2", 2878 "EventName": "LOAD_DISPATCH.RS_DELAYED", 2879 "BriefDescription": "Loads dispatched from stage 305", 2880 "PublicDescription": "Loads dispatched from stage 305", 2881 "Counter": "0,1,2,3", 2882 "SampleAfterValue": "2000000", 2883 "MSRIndex": "0", 2884 "MSRValue": "0", 2885 "CounterMask": "0", 2886 "Invert": "0", 2887 "AnyThread": "0", 2888 "EdgeDetect": "0", 2889 "PEBS": "0", 2890 "Offcore": "0" 2891 }, 2892 { 2893 "EventCode": "0x4C", 2894 "UMask": "0x1", 2895 "EventName": "LOAD_HIT_PRE", 2896 "BriefDescription": "Load operations conflicting with software prefetches", 2897 "PublicDescription": "Load operations conflicting with software prefetches", 2898 "Counter": "0,1", 2899 "SampleAfterValue": "200000", 2900 "MSRIndex": "0", 2901 "MSRValue": "0", 2902 "CounterMask": "0", 2903 "Invert": "0", 2904 "AnyThread": "0", 2905 "EdgeDetect": "0", 2906 "PEBS": "0", 2907 "Offcore": "0" 2908 }, 2909 { 2910 "EventCode": "0x2E", 2911 "UMask": "0x41", 2912 "EventName": "LONGEST_LAT_CACHE.MISS", 2913 "BriefDescription": "Longest latency cache miss", 2914 "PublicDescription": "Longest latency cache miss", 2915 "Counter": "0,1,2,3", 2916 "SampleAfterValue": "100000", 2917 "MSRIndex": "0", 2918 "MSRValue": "0", 2919 "CounterMask": "0", 2920 "Invert": "0", 2921 "AnyThread": "0", 2922 "EdgeDetect": "0", 2923 "PEBS": "0", 2924 "Offcore": "0" 2925 }, 2926 { 2927 "EventCode": "0x2E", 2928 "UMask": "0x4F", 2929 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 2930 "BriefDescription": "Longest latency cache reference", 2931 "PublicDescription": "Longest latency cache reference", 2932 "Counter": "0,1,2,3", 2933 "SampleAfterValue": "200000", 2934 "MSRIndex": "0", 2935 "MSRValue": "0", 2936 "CounterMask": "0", 2937 "Invert": "0", 2938 "AnyThread": "0", 2939 "EdgeDetect": "0", 2940 "PEBS": "0", 2941 "Offcore": "0" 2942 }, 2943 { 2944 "EventCode": "0xA8", 2945 "UMask": "0x1", 2946 "EventName": "LSD.ACTIVE", 2947 "BriefDescription": "Cycles when uops were delivered by the LSD", 2948 "PublicDescription": "Cycles when uops were delivered by the LSD", 2949 "Counter": "0,1,2,3", 2950 "SampleAfterValue": "2000000", 2951 "MSRIndex": "0", 2952 "MSRValue": "0", 2953 "CounterMask": "1", 2954 "Invert": "0", 2955 "AnyThread": "0", 2956 "EdgeDetect": "0", 2957 "PEBS": "0", 2958 "Offcore": "0" 2959 }, 2960 { 2961 "EventCode": "0xA8", 2962 "UMask": "0x1", 2963 "EventName": "LSD.INACTIVE", 2964 "BriefDescription": "Cycles no uops were delivered by the LSD", 2965 "PublicDescription": "Cycles no uops were delivered by the LSD", 2966 "Counter": "0,1,2,3", 2967 "SampleAfterValue": "2000000", 2968 "MSRIndex": "0", 2969 "MSRValue": "0", 2970 "CounterMask": "1", 2971 "Invert": "1", 2972 "AnyThread": "0", 2973 "EdgeDetect": "0", 2974 "PEBS": "0", 2975 "Offcore": "0" 2976 }, 2977 { 2978 "EventCode": "0x20", 2979 "UMask": "0x1", 2980 "EventName": "LSD_OVERFLOW", 2981 "BriefDescription": "Loops that can't stream from the instruction queue", 2982 "PublicDescription": "Loops that can't stream from the instruction queue", 2983 "Counter": "0,1,2,3", 2984 "SampleAfterValue": "2000000", 2985 "MSRIndex": "0", 2986 "MSRValue": "0", 2987 "CounterMask": "0", 2988 "Invert": "0", 2989 "AnyThread": "0", 2990 "EdgeDetect": "0", 2991 "PEBS": "0", 2992 "Offcore": "0" 2993 }, 2994 { 2995 "EventCode": "0xC3", 2996 "UMask": "0x1", 2997 "EventName": "MACHINE_CLEARS.CYCLES", 2998 "BriefDescription": "Cycles machine clear asserted", 2999 "PublicDescription": "Cycles machine clear asserted", 3000 "Counter": "0,1,2,3", 3001 "SampleAfterValue": "20000", 3002 "MSRIndex": "0", 3003 "MSRValue": "0", 3004 "CounterMask": "0", 3005 "Invert": "0", 3006 "AnyThread": "0", 3007 "EdgeDetect": "0", 3008 "PEBS": "0", 3009 "Offcore": "0" 3010 }, 3011 { 3012 "EventCode": "0xC3", 3013 "UMask": "0x2", 3014 "EventName": "MACHINE_CLEARS.MEM_ORDER", 3015 "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts", 3016 "PublicDescription": "Execution pipeline restart due to Memory ordering conflicts", 3017 "Counter": "0,1,2,3", 3018 "SampleAfterValue": "20000", 3019 "MSRIndex": "0", 3020 "MSRValue": "0", 3021 "CounterMask": "0", 3022 "Invert": "0", 3023 "AnyThread": "0", 3024 "EdgeDetect": "0", 3025 "PEBS": "0", 3026 "Offcore": "0" 3027 }, 3028 { 3029 "EventCode": "0xC3", 3030 "UMask": "0x4", 3031 "EventName": "MACHINE_CLEARS.SMC", 3032 "BriefDescription": "Self-Modifying Code detected", 3033 "PublicDescription": "Self-Modifying Code detected", 3034 "Counter": "0,1,2,3", 3035 "SampleAfterValue": "20000", 3036 "MSRIndex": "0", 3037 "MSRValue": "0", 3038 "CounterMask": "0", 3039 "Invert": "0", 3040 "AnyThread": "0", 3041 "EdgeDetect": "0", 3042 "PEBS": "0", 3043 "Offcore": "0" 3044 }, 3045 { 3046 "EventCode": "0xD0", 3047 "UMask": "0x1", 3048 "EventName": "MACRO_INSTS.DECODED", 3049 "BriefDescription": "Instructions decoded", 3050 "PublicDescription": "Instructions decoded", 3051 "Counter": "0,1,2,3", 3052 "SampleAfterValue": "2000000", 3053 "MSRIndex": "0", 3054 "MSRValue": "0", 3055 "CounterMask": "0", 3056 "Invert": "0", 3057 "AnyThread": "0", 3058 "EdgeDetect": "0", 3059 "PEBS": "0", 3060 "Offcore": "0" 3061 }, 3062 { 3063 "EventCode": "0xA6", 3064 "UMask": "0x1", 3065 "EventName": "MACRO_INSTS.FUSIONS_DECODED", 3066 "BriefDescription": "Macro-fused instructions decoded", 3067 "PublicDescription": "Macro-fused instructions decoded", 3068 "Counter": "0,1,2,3", 3069 "SampleAfterValue": "2000000", 3070 "MSRIndex": "0", 3071 "MSRValue": "0", 3072 "CounterMask": "0", 3073 "Invert": "0", 3074 "AnyThread": "0", 3075 "EdgeDetect": "0", 3076 "PEBS": "0", 3077 "Offcore": "0" 3078 }, 3079 { 3080 "EventCode": "0xB", 3081 "UMask": "0x1", 3082 "EventName": "MEM_INST_RETIRED.LOADS", 3083 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 3084 "PublicDescription": "Instructions retired which contains a load (Precise Event)", 3085 "Counter": "0,1,2,3", 3086 "SampleAfterValue": "2000000", 3087 "MSRIndex": "0", 3088 "MSRValue": "0", 3089 "CounterMask": "0", 3090 "Invert": "0", 3091 "AnyThread": "0", 3092 "EdgeDetect": "0", 3093 "PEBS": "1", 3094 "Offcore": "0" 3095 }, 3096 { 3097 "EventCode": "0xB", 3098 "UMask": "0x2", 3099 "EventName": "MEM_INST_RETIRED.STORES", 3100 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 3101 "PublicDescription": "Instructions retired which contains a store (Precise Event)", 3102 "Counter": "0,1,2,3", 3103 "SampleAfterValue": "2000000", 3104 "MSRIndex": "0", 3105 "MSRValue": "0", 3106 "CounterMask": "0", 3107 "Invert": "0", 3108 "AnyThread": "0", 3109 "EdgeDetect": "0", 3110 "PEBS": "1", 3111 "Offcore": "0" 3112 }, 3113 { 3114 "EventCode": "0xCB", 3115 "UMask": "0x80", 3116 "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", 3117 "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", 3118 "PublicDescription": "Retired loads that miss the DTLB (Precise Event)", 3119 "Counter": "0,1,2,3", 3120 "SampleAfterValue": "200000", 3121 "MSRIndex": "0", 3122 "MSRValue": "0", 3123 "CounterMask": "0", 3124 "Invert": "0", 3125 "AnyThread": "0", 3126 "EdgeDetect": "0", 3127 "PEBS": "1", 3128 "Offcore": "0" 3129 }, 3130 { 3131 "EventCode": "0xCB", 3132 "UMask": "0x40", 3133 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 3134 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 3135 "PublicDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 3136 "Counter": "0,1,2,3", 3137 "SampleAfterValue": "200000", 3138 "MSRIndex": "0", 3139 "MSRValue": "0", 3140 "CounterMask": "0", 3141 "Invert": "0", 3142 "AnyThread": "0", 3143 "EdgeDetect": "0", 3144 "PEBS": "1", 3145 "Offcore": "0" 3146 }, 3147 { 3148 "EventCode": "0xCB", 3149 "UMask": "0x1", 3150 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 3151 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 3152 "PublicDescription": "Retired loads that hit the L1 data cache (Precise Event)", 3153 "Counter": "0,1,2,3", 3154 "SampleAfterValue": "2000000", 3155 "MSRIndex": "0", 3156 "MSRValue": "0", 3157 "CounterMask": "0", 3158 "Invert": "0", 3159 "AnyThread": "0", 3160 "EdgeDetect": "0", 3161 "PEBS": "1", 3162 "Offcore": "0" 3163 }, 3164 { 3165 "EventCode": "0xCB", 3166 "UMask": "0x2", 3167 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 3168 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 3169 "PublicDescription": "Retired loads that hit the L2 cache (Precise Event)", 3170 "Counter": "0,1,2,3", 3171 "SampleAfterValue": "200000", 3172 "MSRIndex": "0", 3173 "MSRValue": "0", 3174 "CounterMask": "0", 3175 "Invert": "0", 3176 "AnyThread": "0", 3177 "EdgeDetect": "0", 3178 "PEBS": "1", 3179 "Offcore": "0" 3180 }, 3181 { 3182 "EventCode": "0xCB", 3183 "UMask": "0x10", 3184 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 3185 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 3186 "PublicDescription": "Retired loads that miss the LLC cache (Precise Event)", 3187 "Counter": "0,1,2,3", 3188 "SampleAfterValue": "10000", 3189 "MSRIndex": "0", 3190 "MSRValue": "0", 3191 "CounterMask": "0", 3192 "Invert": "0", 3193 "AnyThread": "0", 3194 "EdgeDetect": "0", 3195 "PEBS": "1", 3196 "Offcore": "0" 3197 }, 3198 { 3199 "EventCode": "0xCB", 3200 "UMask": "0x4", 3201 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 3202 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 3203 "PublicDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 3204 "Counter": "0,1,2,3", 3205 "SampleAfterValue": "40000", 3206 "MSRIndex": "0", 3207 "MSRValue": "0", 3208 "CounterMask": "0", 3209 "Invert": "0", 3210 "AnyThread": "0", 3211 "EdgeDetect": "0", 3212 "PEBS": "1", 3213 "Offcore": "0" 3214 }, 3215 { 3216 "EventCode": "0xCB", 3217 "UMask": "0x8", 3218 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 3219 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 3220 "PublicDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 3221 "Counter": "0,1,2,3", 3222 "SampleAfterValue": "40000", 3223 "MSRIndex": "0", 3224 "MSRValue": "0", 3225 "CounterMask": "0", 3226 "Invert": "0", 3227 "AnyThread": "0", 3228 "EdgeDetect": "0", 3229 "PEBS": "1", 3230 "Offcore": "0" 3231 }, 3232 { 3233 "EventCode": "0xC", 3234 "UMask": "0x1", 3235 "EventName": "MEM_STORE_RETIRED.DTLB_MISS", 3236 "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", 3237 "PublicDescription": "Retired stores that miss the DTLB (Precise Event)", 3238 "Counter": "0,1,2,3", 3239 "SampleAfterValue": "200000", 3240 "MSRIndex": "0", 3241 "MSRValue": "0", 3242 "CounterMask": "0", 3243 "Invert": "0", 3244 "AnyThread": "0", 3245 "EdgeDetect": "0", 3246 "PEBS": "1", 3247 "Offcore": "0" 3248 }, 3249 { 3250 "EventCode": "0xB0", 3251 "UMask": "0x40", 3252 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 3253 "BriefDescription": "Offcore L1 data cache writebacks", 3254 "PublicDescription": "Offcore L1 data cache writebacks", 3255 "Counter": "0,1,2,3", 3256 "SampleAfterValue": "100000", 3257 "MSRIndex": "0", 3258 "MSRValue": "0", 3259 "CounterMask": "0", 3260 "Invert": "0", 3261 "AnyThread": "0", 3262 "EdgeDetect": "0", 3263 "PEBS": "0", 3264 "Offcore": "0" 3265 }, 3266 { 3267 "EventCode": "0xB2", 3268 "UMask": "0x1", 3269 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 3270 "BriefDescription": "Offcore requests blocked due to Super Queue full", 3271 "PublicDescription": "Offcore requests blocked due to Super Queue full", 3272 "Counter": "0,1,2,3", 3273 "SampleAfterValue": "100000", 3274 "MSRIndex": "0", 3275 "MSRValue": "0", 3276 "CounterMask": "0", 3277 "Invert": "0", 3278 "AnyThread": "0", 3279 "EdgeDetect": "0", 3280 "PEBS": "0", 3281 "Offcore": "0" 3282 }, 3283 { 3284 "EventCode": "0x7", 3285 "UMask": "0x1", 3286 "EventName": "PARTIAL_ADDRESS_ALIAS", 3287 "BriefDescription": "False dependencies due to partial address aliasing", 3288 "PublicDescription": "False dependencies due to partial address aliasing", 3289 "Counter": "0,1,2,3", 3290 "SampleAfterValue": "200000", 3291 "MSRIndex": "0", 3292 "MSRValue": "0", 3293 "CounterMask": "0", 3294 "Invert": "0", 3295 "AnyThread": "0", 3296 "EdgeDetect": "0", 3297 "PEBS": "0", 3298 "Offcore": "0" 3299 }, 3300 { 3301 "EventCode": "0xD2", 3302 "UMask": "0xF", 3303 "EventName": "RAT_STALLS.ANY", 3304 "BriefDescription": "All RAT stall cycles", 3305 "PublicDescription": "All RAT stall cycles", 3306 "Counter": "0,1,2,3", 3307 "SampleAfterValue": "2000000", 3308 "MSRIndex": "0", 3309 "MSRValue": "0", 3310 "CounterMask": "0", 3311 "Invert": "0", 3312 "AnyThread": "0", 3313 "EdgeDetect": "0", 3314 "PEBS": "0", 3315 "Offcore": "0" 3316 }, 3317 { 3318 "EventCode": "0xD2", 3319 "UMask": "0x1", 3320 "EventName": "RAT_STALLS.FLAGS", 3321 "BriefDescription": "Flag stall cycles", 3322 "PublicDescription": "Flag stall cycles", 3323 "Counter": "0,1,2,3", 3324 "SampleAfterValue": "2000000", 3325 "MSRIndex": "0", 3326 "MSRValue": "0", 3327 "CounterMask": "0", 3328 "Invert": "0", 3329 "AnyThread": "0", 3330 "EdgeDetect": "0", 3331 "PEBS": "0", 3332 "Offcore": "0" 3333 }, 3334 { 3335 "EventCode": "0xD2", 3336 "UMask": "0x2", 3337 "EventName": "RAT_STALLS.REGISTERS", 3338 "BriefDescription": "Partial register stall cycles", 3339 "PublicDescription": "Partial register stall cycles", 3340 "Counter": "0,1,2,3", 3341 "SampleAfterValue": "2000000", 3342 "MSRIndex": "0", 3343 "MSRValue": "0", 3344 "CounterMask": "0", 3345 "Invert": "0", 3346 "AnyThread": "0", 3347 "EdgeDetect": "0", 3348 "PEBS": "0", 3349 "Offcore": "0" 3350 }, 3351 { 3352 "EventCode": "0xD2", 3353 "UMask": "0x4", 3354 "EventName": "RAT_STALLS.ROB_READ_PORT", 3355 "BriefDescription": "ROB read port stalls cycles", 3356 "PublicDescription": "ROB read port stalls cycles", 3357 "Counter": "0,1,2,3", 3358 "SampleAfterValue": "2000000", 3359 "MSRIndex": "0", 3360 "MSRValue": "0", 3361 "CounterMask": "0", 3362 "Invert": "0", 3363 "AnyThread": "0", 3364 "EdgeDetect": "0", 3365 "PEBS": "0", 3366 "Offcore": "0" 3367 }, 3368 { 3369 "EventCode": "0xD2", 3370 "UMask": "0x8", 3371 "EventName": "RAT_STALLS.SCOREBOARD", 3372 "BriefDescription": "Scoreboard stall cycles", 3373 "PublicDescription": "Scoreboard stall cycles", 3374 "Counter": "0,1,2,3", 3375 "SampleAfterValue": "2000000", 3376 "MSRIndex": "0", 3377 "MSRValue": "0", 3378 "CounterMask": "0", 3379 "Invert": "0", 3380 "AnyThread": "0", 3381 "EdgeDetect": "0", 3382 "PEBS": "0", 3383 "Offcore": "0" 3384 }, 3385 { 3386 "EventCode": "0xA2", 3387 "UMask": "0x1", 3388 "EventName": "RESOURCE_STALLS.ANY", 3389 "BriefDescription": "Resource related stall cycles", 3390 "PublicDescription": "Resource related stall cycles", 3391 "Counter": "0,1,2,3", 3392 "SampleAfterValue": "2000000", 3393 "MSRIndex": "0", 3394 "MSRValue": "0", 3395 "CounterMask": "0", 3396 "Invert": "0", 3397 "AnyThread": "0", 3398 "EdgeDetect": "0", 3399 "PEBS": "0", 3400 "Offcore": "0" 3401 }, 3402 { 3403 "EventCode": "0xA2", 3404 "UMask": "0x20", 3405 "EventName": "RESOURCE_STALLS.FPCW", 3406 "BriefDescription": "FPU control word write stall cycles", 3407 "PublicDescription": "FPU control word write stall cycles", 3408 "Counter": "0,1,2,3", 3409 "SampleAfterValue": "2000000", 3410 "MSRIndex": "0", 3411 "MSRValue": "0", 3412 "CounterMask": "0", 3413 "Invert": "0", 3414 "AnyThread": "0", 3415 "EdgeDetect": "0", 3416 "PEBS": "0", 3417 "Offcore": "0" 3418 }, 3419 { 3420 "EventCode": "0xA2", 3421 "UMask": "0x2", 3422 "EventName": "RESOURCE_STALLS.LOAD", 3423 "BriefDescription": "Load buffer stall cycles", 3424 "PublicDescription": "Load buffer stall cycles", 3425 "Counter": "0,1,2,3", 3426 "SampleAfterValue": "2000000", 3427 "MSRIndex": "0", 3428 "MSRValue": "0", 3429 "CounterMask": "0", 3430 "Invert": "0", 3431 "AnyThread": "0", 3432 "EdgeDetect": "0", 3433 "PEBS": "0", 3434 "Offcore": "0" 3435 }, 3436 { 3437 "EventCode": "0xA2", 3438 "UMask": "0x40", 3439 "EventName": "RESOURCE_STALLS.MXCSR", 3440 "BriefDescription": "MXCSR rename stall cycles", 3441 "PublicDescription": "MXCSR rename stall cycles", 3442 "Counter": "0,1,2,3", 3443 "SampleAfterValue": "2000000", 3444 "MSRIndex": "0", 3445 "MSRValue": "0", 3446 "CounterMask": "0", 3447 "Invert": "0", 3448 "AnyThread": "0", 3449 "EdgeDetect": "0", 3450 "PEBS": "0", 3451 "Offcore": "0" 3452 }, 3453 { 3454 "EventCode": "0xA2", 3455 "UMask": "0x80", 3456 "EventName": "RESOURCE_STALLS.OTHER", 3457 "BriefDescription": "Other Resource related stall cycles", 3458 "PublicDescription": "Other Resource related stall cycles", 3459 "Counter": "0,1,2,3", 3460 "SampleAfterValue": "2000000", 3461 "MSRIndex": "0", 3462 "MSRValue": "0", 3463 "CounterMask": "0", 3464 "Invert": "0", 3465 "AnyThread": "0", 3466 "EdgeDetect": "0", 3467 "PEBS": "0", 3468 "Offcore": "0" 3469 }, 3470 { 3471 "EventCode": "0xA2", 3472 "UMask": "0x10", 3473 "EventName": "RESOURCE_STALLS.ROB_FULL", 3474 "BriefDescription": "ROB full stall cycles", 3475 "PublicDescription": "ROB full stall cycles", 3476 "Counter": "0,1,2,3", 3477 "SampleAfterValue": "2000000", 3478 "MSRIndex": "0", 3479 "MSRValue": "0", 3480 "CounterMask": "0", 3481 "Invert": "0", 3482 "AnyThread": "0", 3483 "EdgeDetect": "0", 3484 "PEBS": "0", 3485 "Offcore": "0" 3486 }, 3487 { 3488 "EventCode": "0xA2", 3489 "UMask": "0x4", 3490 "EventName": "RESOURCE_STALLS.RS_FULL", 3491 "BriefDescription": "Reservation Station full stall cycles", 3492 "PublicDescription": "Reservation Station full stall cycles", 3493 "Counter": "0,1,2,3", 3494 "SampleAfterValue": "2000000", 3495 "MSRIndex": "0", 3496 "MSRValue": "0", 3497 "CounterMask": "0", 3498 "Invert": "0", 3499 "AnyThread": "0", 3500 "EdgeDetect": "0", 3501 "PEBS": "0", 3502 "Offcore": "0" 3503 }, 3504 { 3505 "EventCode": "0xA2", 3506 "UMask": "0x8", 3507 "EventName": "RESOURCE_STALLS.STORE", 3508 "BriefDescription": "Store buffer stall cycles", 3509 "PublicDescription": "Store buffer stall cycles", 3510 "Counter": "0,1,2,3", 3511 "SampleAfterValue": "2000000", 3512 "MSRIndex": "0", 3513 "MSRValue": "0", 3514 "CounterMask": "0", 3515 "Invert": "0", 3516 "AnyThread": "0", 3517 "EdgeDetect": "0", 3518 "PEBS": "0", 3519 "Offcore": "0" 3520 }, 3521 { 3522 "EventCode": "0x4", 3523 "UMask": "0x7", 3524 "EventName": "SB_DRAIN.ANY", 3525 "BriefDescription": "All Store buffer stall cycles", 3526 "PublicDescription": "All Store buffer stall cycles", 3527 "Counter": "0,1,2,3", 3528 "SampleAfterValue": "200000", 3529 "MSRIndex": "0", 3530 "MSRValue": "0", 3531 "CounterMask": "0", 3532 "Invert": "0", 3533 "AnyThread": "0", 3534 "EdgeDetect": "0", 3535 "PEBS": "0", 3536 "Offcore": "0" 3537 }, 3538 { 3539 "EventCode": "0xD4", 3540 "UMask": "0x1", 3541 "EventName": "SEG_RENAME_STALLS", 3542 "BriefDescription": "Segment rename stall cycles", 3543 "PublicDescription": "Segment rename stall cycles", 3544 "Counter": "0,1,2,3", 3545 "SampleAfterValue": "2000000", 3546 "MSRIndex": "0", 3547 "MSRValue": "0", 3548 "CounterMask": "0", 3549 "Invert": "0", 3550 "AnyThread": "0", 3551 "EdgeDetect": "0", 3552 "PEBS": "0", 3553 "Offcore": "0" 3554 }, 3555 { 3556 "EventCode": "0x12", 3557 "UMask": "0x4", 3558 "EventName": "SIMD_INT_128.PACK", 3559 "BriefDescription": "128 bit SIMD integer pack operations", 3560 "PublicDescription": "128 bit SIMD integer pack operations", 3561 "Counter": "0,1,2,3", 3562 "SampleAfterValue": "200000", 3563 "MSRIndex": "0", 3564 "MSRValue": "0", 3565 "CounterMask": "0", 3566 "Invert": "0", 3567 "AnyThread": "0", 3568 "EdgeDetect": "0", 3569 "PEBS": "0", 3570 "Offcore": "0" 3571 }, 3572 { 3573 "EventCode": "0x12", 3574 "UMask": "0x20", 3575 "EventName": "SIMD_INT_128.PACKED_ARITH", 3576 "BriefDescription": "128 bit SIMD integer arithmetic operations", 3577 "PublicDescription": "128 bit SIMD integer arithmetic operations", 3578 "Counter": "0,1,2,3", 3579 "SampleAfterValue": "200000", 3580 "MSRIndex": "0", 3581 "MSRValue": "0", 3582 "CounterMask": "0", 3583 "Invert": "0", 3584 "AnyThread": "0", 3585 "EdgeDetect": "0", 3586 "PEBS": "0", 3587 "Offcore": "0" 3588 }, 3589 { 3590 "EventCode": "0x12", 3591 "UMask": "0x10", 3592 "EventName": "SIMD_INT_128.PACKED_LOGICAL", 3593 "BriefDescription": "128 bit SIMD integer logical operations", 3594 "PublicDescription": "128 bit SIMD integer logical operations", 3595 "Counter": "0,1,2,3", 3596 "SampleAfterValue": "200000", 3597 "MSRIndex": "0", 3598 "MSRValue": "0", 3599 "CounterMask": "0", 3600 "Invert": "0", 3601 "AnyThread": "0", 3602 "EdgeDetect": "0", 3603 "PEBS": "0", 3604 "Offcore": "0" 3605 }, 3606 { 3607 "EventCode": "0x12", 3608 "UMask": "0x1", 3609 "EventName": "SIMD_INT_128.PACKED_MPY", 3610 "BriefDescription": "128 bit SIMD integer multiply operations", 3611 "PublicDescription": "128 bit SIMD integer multiply operations", 3612 "Counter": "0,1,2,3", 3613 "SampleAfterValue": "200000", 3614 "MSRIndex": "0", 3615 "MSRValue": "0", 3616 "CounterMask": "0", 3617 "Invert": "0", 3618 "AnyThread": "0", 3619 "EdgeDetect": "0", 3620 "PEBS": "0", 3621 "Offcore": "0" 3622 }, 3623 { 3624 "EventCode": "0x12", 3625 "UMask": "0x2", 3626 "EventName": "SIMD_INT_128.PACKED_SHIFT", 3627 "BriefDescription": "128 bit SIMD integer shift operations", 3628 "PublicDescription": "128 bit SIMD integer shift operations", 3629 "Counter": "0,1,2,3", 3630 "SampleAfterValue": "200000", 3631 "MSRIndex": "0", 3632 "MSRValue": "0", 3633 "CounterMask": "0", 3634 "Invert": "0", 3635 "AnyThread": "0", 3636 "EdgeDetect": "0", 3637 "PEBS": "0", 3638 "Offcore": "0" 3639 }, 3640 { 3641 "EventCode": "0x12", 3642 "UMask": "0x40", 3643 "EventName": "SIMD_INT_128.SHUFFLE_MOVE", 3644 "BriefDescription": "128 bit SIMD integer shuffle/move operations", 3645 "PublicDescription": "128 bit SIMD integer shuffle/move operations", 3646 "Counter": "0,1,2,3", 3647 "SampleAfterValue": "200000", 3648 "MSRIndex": "0", 3649 "MSRValue": "0", 3650 "CounterMask": "0", 3651 "Invert": "0", 3652 "AnyThread": "0", 3653 "EdgeDetect": "0", 3654 "PEBS": "0", 3655 "Offcore": "0" 3656 }, 3657 { 3658 "EventCode": "0x12", 3659 "UMask": "0x8", 3660 "EventName": "SIMD_INT_128.UNPACK", 3661 "BriefDescription": "128 bit SIMD integer unpack operations", 3662 "PublicDescription": "128 bit SIMD integer unpack operations", 3663 "Counter": "0,1,2,3", 3664 "SampleAfterValue": "200000", 3665 "MSRIndex": "0", 3666 "MSRValue": "0", 3667 "CounterMask": "0", 3668 "Invert": "0", 3669 "AnyThread": "0", 3670 "EdgeDetect": "0", 3671 "PEBS": "0", 3672 "Offcore": "0" 3673 }, 3674 { 3675 "EventCode": "0xFD", 3676 "UMask": "0x4", 3677 "EventName": "SIMD_INT_64.PACK", 3678 "BriefDescription": "SIMD integer 64 bit pack operations", 3679 "PublicDescription": "SIMD integer 64 bit pack operations", 3680 "Counter": "0,1,2,3", 3681 "SampleAfterValue": "200000", 3682 "MSRIndex": "0", 3683 "MSRValue": "0", 3684 "CounterMask": "0", 3685 "Invert": "0", 3686 "AnyThread": "0", 3687 "EdgeDetect": "0", 3688 "PEBS": "0", 3689 "Offcore": "0" 3690 }, 3691 { 3692 "EventCode": "0xFD", 3693 "UMask": "0x20", 3694 "EventName": "SIMD_INT_64.PACKED_ARITH", 3695 "BriefDescription": "SIMD integer 64 bit arithmetic operations", 3696 "PublicDescription": "SIMD integer 64 bit arithmetic operations", 3697 "Counter": "0,1,2,3", 3698 "SampleAfterValue": "200000", 3699 "MSRIndex": "0", 3700 "MSRValue": "0", 3701 "CounterMask": "0", 3702 "Invert": "0", 3703 "AnyThread": "0", 3704 "EdgeDetect": "0", 3705 "PEBS": "0", 3706 "Offcore": "0" 3707 }, 3708 { 3709 "EventCode": "0xFD", 3710 "UMask": "0x10", 3711 "EventName": "SIMD_INT_64.PACKED_LOGICAL", 3712 "BriefDescription": "SIMD integer 64 bit logical operations", 3713 "PublicDescription": "SIMD integer 64 bit logical operations", 3714 "Counter": "0,1,2,3", 3715 "SampleAfterValue": "200000", 3716 "MSRIndex": "0", 3717 "MSRValue": "0", 3718 "CounterMask": "0", 3719 "Invert": "0", 3720 "AnyThread": "0", 3721 "EdgeDetect": "0", 3722 "PEBS": "0", 3723 "Offcore": "0" 3724 }, 3725 { 3726 "EventCode": "0xFD", 3727 "UMask": "0x1", 3728 "EventName": "SIMD_INT_64.PACKED_MPY", 3729 "BriefDescription": "SIMD integer 64 bit packed multiply operations", 3730 "PublicDescription": "SIMD integer 64 bit packed multiply operations", 3731 "Counter": "0,1,2,3", 3732 "SampleAfterValue": "200000", 3733 "MSRIndex": "0", 3734 "MSRValue": "0", 3735 "CounterMask": "0", 3736 "Invert": "0", 3737 "AnyThread": "0", 3738 "EdgeDetect": "0", 3739 "PEBS": "0", 3740 "Offcore": "0" 3741 }, 3742 { 3743 "EventCode": "0xFD", 3744 "UMask": "0x2", 3745 "EventName": "SIMD_INT_64.PACKED_SHIFT", 3746 "BriefDescription": "SIMD integer 64 bit shift operations", 3747 "PublicDescription": "SIMD integer 64 bit shift operations", 3748 "Counter": "0,1,2,3", 3749 "SampleAfterValue": "200000", 3750 "MSRIndex": "0", 3751 "MSRValue": "0", 3752 "CounterMask": "0", 3753 "Invert": "0", 3754 "AnyThread": "0", 3755 "EdgeDetect": "0", 3756 "PEBS": "0", 3757 "Offcore": "0" 3758 }, 3759 { 3760 "EventCode": "0xFD", 3761 "UMask": "0x40", 3762 "EventName": "SIMD_INT_64.SHUFFLE_MOVE", 3763 "BriefDescription": "SIMD integer 64 bit shuffle/move operations", 3764 "PublicDescription": "SIMD integer 64 bit shuffle/move operations", 3765 "Counter": "0,1,2,3", 3766 "SampleAfterValue": "200000", 3767 "MSRIndex": "0", 3768 "MSRValue": "0", 3769 "CounterMask": "0", 3770 "Invert": "0", 3771 "AnyThread": "0", 3772 "EdgeDetect": "0", 3773 "PEBS": "0", 3774 "Offcore": "0" 3775 }, 3776 { 3777 "EventCode": "0xFD", 3778 "UMask": "0x8", 3779 "EventName": "SIMD_INT_64.UNPACK", 3780 "BriefDescription": "SIMD integer 64 bit unpack operations", 3781 "PublicDescription": "SIMD integer 64 bit unpack operations", 3782 "Counter": "0,1,2,3", 3783 "SampleAfterValue": "200000", 3784 "MSRIndex": "0", 3785 "MSRValue": "0", 3786 "CounterMask": "0", 3787 "Invert": "0", 3788 "AnyThread": "0", 3789 "EdgeDetect": "0", 3790 "PEBS": "0", 3791 "Offcore": "0" 3792 }, 3793 { 3794 "EventCode": "0xB8", 3795 "UMask": "0x1", 3796 "EventName": "SNOOP_RESPONSE.HIT", 3797 "BriefDescription": "Thread responded HIT to snoop", 3798 "PublicDescription": "Thread responded HIT to snoop", 3799 "Counter": "0,1,2,3", 3800 "SampleAfterValue": "100000", 3801 "MSRIndex": "0", 3802 "MSRValue": "0", 3803 "CounterMask": "0", 3804 "Invert": "0", 3805 "AnyThread": "0", 3806 "EdgeDetect": "0", 3807 "PEBS": "0", 3808 "Offcore": "0" 3809 }, 3810 { 3811 "EventCode": "0xB8", 3812 "UMask": "0x2", 3813 "EventName": "SNOOP_RESPONSE.HITE", 3814 "BriefDescription": "Thread responded HITE to snoop", 3815 "PublicDescription": "Thread responded HITE to snoop", 3816 "Counter": "0,1,2,3", 3817 "SampleAfterValue": "100000", 3818 "MSRIndex": "0", 3819 "MSRValue": "0", 3820 "CounterMask": "0", 3821 "Invert": "0", 3822 "AnyThread": "0", 3823 "EdgeDetect": "0", 3824 "PEBS": "0", 3825 "Offcore": "0" 3826 }, 3827 { 3828 "EventCode": "0xB8", 3829 "UMask": "0x4", 3830 "EventName": "SNOOP_RESPONSE.HITM", 3831 "BriefDescription": "Thread responded HITM to snoop", 3832 "PublicDescription": "Thread responded HITM to snoop", 3833 "Counter": "0,1,2,3", 3834 "SampleAfterValue": "100000", 3835 "MSRIndex": "0", 3836 "MSRValue": "0", 3837 "CounterMask": "0", 3838 "Invert": "0", 3839 "AnyThread": "0", 3840 "EdgeDetect": "0", 3841 "PEBS": "0", 3842 "Offcore": "0" 3843 }, 3844 { 3845 "EventCode": "0xF6", 3846 "UMask": "0x1", 3847 "EventName": "SQ_FULL_STALL_CYCLES", 3848 "BriefDescription": "Super Queue full stall cycles", 3849 "PublicDescription": "Super Queue full stall cycles", 3850 "Counter": "0,1,2,3", 3851 "SampleAfterValue": "2000000", 3852 "MSRIndex": "0", 3853 "MSRValue": "0", 3854 "CounterMask": "0", 3855 "Invert": "0", 3856 "AnyThread": "0", 3857 "EdgeDetect": "0", 3858 "PEBS": "0", 3859 "Offcore": "0" 3860 }, 3861 { 3862 "EventCode": "0xF4", 3863 "UMask": "0x10", 3864 "EventName": "SQ_MISC.SPLIT_LOCK", 3865 "BriefDescription": "Super Queue lock splits across a cache line", 3866 "PublicDescription": "Super Queue lock splits across a cache line", 3867 "Counter": "0,1,2,3", 3868 "SampleAfterValue": "2000000", 3869 "MSRIndex": "0", 3870 "MSRValue": "0", 3871 "CounterMask": "0", 3872 "Invert": "0", 3873 "AnyThread": "0", 3874 "EdgeDetect": "0", 3875 "PEBS": "0", 3876 "Offcore": "0" 3877 }, 3878 { 3879 "EventCode": "0xC7", 3880 "UMask": "0x4", 3881 "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", 3882 "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)", 3883 "PublicDescription": "SIMD Packed-Double Uops retired (Precise Event)", 3884 "Counter": "0,1,2,3", 3885 "SampleAfterValue": "200000", 3886 "MSRIndex": "0", 3887 "MSRValue": "0", 3888 "CounterMask": "0", 3889 "Invert": "0", 3890 "AnyThread": "0", 3891 "EdgeDetect": "0", 3892 "PEBS": "1", 3893 "Offcore": "0" 3894 }, 3895 { 3896 "EventCode": "0xC7", 3897 "UMask": "0x1", 3898 "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", 3899 "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)", 3900 "PublicDescription": "SIMD Packed-Single Uops retired (Precise Event)", 3901 "Counter": "0,1,2,3", 3902 "SampleAfterValue": "200000", 3903 "MSRIndex": "0", 3904 "MSRValue": "0", 3905 "CounterMask": "0", 3906 "Invert": "0", 3907 "AnyThread": "0", 3908 "EdgeDetect": "0", 3909 "PEBS": "1", 3910 "Offcore": "0" 3911 }, 3912 { 3913 "EventCode": "0xC7", 3914 "UMask": "0x8", 3915 "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", 3916 "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)", 3917 "PublicDescription": "SIMD Scalar-Double Uops retired (Precise Event)", 3918 "Counter": "0,1,2,3", 3919 "SampleAfterValue": "200000", 3920 "MSRIndex": "0", 3921 "MSRValue": "0", 3922 "CounterMask": "0", 3923 "Invert": "0", 3924 "AnyThread": "0", 3925 "EdgeDetect": "0", 3926 "PEBS": "1", 3927 "Offcore": "0" 3928 }, 3929 { 3930 "EventCode": "0xC7", 3931 "UMask": "0x2", 3932 "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", 3933 "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)", 3934 "PublicDescription": "SIMD Scalar-Single Uops retired (Precise Event)", 3935 "Counter": "0,1,2,3", 3936 "SampleAfterValue": "200000", 3937 "MSRIndex": "0", 3938 "MSRValue": "0", 3939 "CounterMask": "0", 3940 "Invert": "0", 3941 "AnyThread": "0", 3942 "EdgeDetect": "0", 3943 "PEBS": "1", 3944 "Offcore": "0" 3945 }, 3946 { 3947 "EventCode": "0xC7", 3948 "UMask": "0x10", 3949 "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", 3950 "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)", 3951 "PublicDescription": "SIMD Vector Integer Uops retired (Precise Event)", 3952 "Counter": "0,1,2,3", 3953 "SampleAfterValue": "200000", 3954 "MSRIndex": "0", 3955 "MSRValue": "0", 3956 "CounterMask": "0", 3957 "Invert": "0", 3958 "AnyThread": "0", 3959 "EdgeDetect": "0", 3960 "PEBS": "1", 3961 "Offcore": "0" 3962 }, 3963 { 3964 "EventCode": "0x6", 3965 "UMask": "0x4", 3966 "EventName": "STORE_BLOCKS.AT_RET", 3967 "BriefDescription": "Loads delayed with at-Retirement block code", 3968 "PublicDescription": "Loads delayed with at-Retirement block code", 3969 "Counter": "0,1,2,3", 3970 "SampleAfterValue": "200000", 3971 "MSRIndex": "0", 3972 "MSRValue": "0", 3973 "CounterMask": "0", 3974 "Invert": "0", 3975 "AnyThread": "0", 3976 "EdgeDetect": "0", 3977 "PEBS": "0", 3978 "Offcore": "0" 3979 }, 3980 { 3981 "EventCode": "0x6", 3982 "UMask": "0x8", 3983 "EventName": "STORE_BLOCKS.L1D_BLOCK", 3984 "BriefDescription": "Cacheable loads delayed with L1D block code", 3985 "PublicDescription": "Cacheable loads delayed with L1D block code", 3986 "Counter": "0,1,2,3", 3987 "SampleAfterValue": "200000", 3988 "MSRIndex": "0", 3989 "MSRValue": "0", 3990 "CounterMask": "0", 3991 "Invert": "0", 3992 "AnyThread": "0", 3993 "EdgeDetect": "0", 3994 "PEBS": "0", 3995 "Offcore": "0" 3996 }, 3997 { 3998 "EventCode": "0x19", 3999 "UMask": "0x1", 4000 "EventName": "TWO_UOP_INSTS_DECODED", 4001 "BriefDescription": "Two Uop instructions decoded", 4002 "PublicDescription": "Two Uop instructions decoded", 4003 "Counter": "0,1,2,3", 4004 "SampleAfterValue": "2000000", 4005 "MSRIndex": "0", 4006 "MSRValue": "0", 4007 "CounterMask": "0", 4008 "Invert": "0", 4009 "AnyThread": "0", 4010 "EdgeDetect": "0", 4011 "PEBS": "0", 4012 "Offcore": "0" 4013 }, 4014 { 4015 "EventCode": "0xDB", 4016 "UMask": "0x1", 4017 "EventName": "UOP_UNFUSION", 4018 "BriefDescription": "Uop unfusions due to FP exceptions", 4019 "PublicDescription": "Uop unfusions due to FP exceptions", 4020 "Counter": "0,1,2,3", 4021 "SampleAfterValue": "2000000", 4022 "MSRIndex": "0", 4023 "MSRValue": "0", 4024 "CounterMask": "0", 4025 "Invert": "0", 4026 "AnyThread": "0", 4027 "EdgeDetect": "0", 4028 "PEBS": "0", 4029 "Offcore": "0" 4030 }, 4031 { 4032 "EventCode": "0xD1", 4033 "UMask": "0x4", 4034 "EventName": "UOPS_DECODED.ESP_FOLDING", 4035 "BriefDescription": "Stack pointer instructions decoded", 4036 "PublicDescription": "Stack pointer instructions decoded", 4037 "Counter": "0,1,2,3", 4038 "SampleAfterValue": "2000000", 4039 "MSRIndex": "0", 4040 "MSRValue": "0", 4041 "CounterMask": "0", 4042 "Invert": "0", 4043 "AnyThread": "0", 4044 "EdgeDetect": "0", 4045 "PEBS": "0", 4046 "Offcore": "0" 4047 }, 4048 { 4049 "EventCode": "0xD1", 4050 "UMask": "0x8", 4051 "EventName": "UOPS_DECODED.ESP_SYNC", 4052 "BriefDescription": "Stack pointer sync operations", 4053 "PublicDescription": "Stack pointer sync operations", 4054 "Counter": "0,1,2,3", 4055 "SampleAfterValue": "2000000", 4056 "MSRIndex": "0", 4057 "MSRValue": "0", 4058 "CounterMask": "0", 4059 "Invert": "0", 4060 "AnyThread": "0", 4061 "EdgeDetect": "0", 4062 "PEBS": "0", 4063 "Offcore": "0" 4064 }, 4065 { 4066 "EventCode": "0xD1", 4067 "UMask": "0x2", 4068 "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", 4069 "BriefDescription": "Uops decoded by Microcode Sequencer", 4070 "PublicDescription": "Uops decoded by Microcode Sequencer", 4071 "Counter": "0,1,2,3", 4072 "SampleAfterValue": "2000000", 4073 "MSRIndex": "0", 4074 "MSRValue": "0", 4075 "CounterMask": "1", 4076 "Invert": "0", 4077 "AnyThread": "0", 4078 "EdgeDetect": "0", 4079 "PEBS": "0", 4080 "Offcore": "0" 4081 }, 4082 { 4083 "EventCode": "0xD1", 4084 "UMask": "0x1", 4085 "EventName": "UOPS_DECODED.STALL_CYCLES", 4086 "BriefDescription": "Cycles no Uops are decoded", 4087 "PublicDescription": "Cycles no Uops are decoded", 4088 "Counter": "0,1,2,3", 4089 "SampleAfterValue": "2000000", 4090 "MSRIndex": "0", 4091 "MSRValue": "0", 4092 "CounterMask": "1", 4093 "Invert": "1", 4094 "AnyThread": "0", 4095 "EdgeDetect": "0", 4096 "PEBS": "0", 4097 "Offcore": "0" 4098 }, 4099 { 4100 "EventCode": "0xB1", 4101 "UMask": "0x3F", 4102 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", 4103 "BriefDescription": "Cycles Uops executed on any port (core count)", 4104 "PublicDescription": "Cycles Uops executed on any port (core count)", 4105 "Counter": "0,1,2,3", 4106 "SampleAfterValue": "2000000", 4107 "MSRIndex": "0", 4108 "MSRValue": "0", 4109 "CounterMask": "1", 4110 "Invert": "0", 4111 "AnyThread": "1", 4112 "EdgeDetect": "0", 4113 "PEBS": "0", 4114 "Offcore": "0" 4115 }, 4116 { 4117 "EventCode": "0xB1", 4118 "UMask": "0x1F", 4119 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", 4120 "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", 4121 "PublicDescription": "Cycles Uops executed on ports 0-4 (core count)", 4122 "Counter": "0,1,2,3", 4123 "SampleAfterValue": "2000000", 4124 "MSRIndex": "0", 4125 "MSRValue": "0", 4126 "CounterMask": "1", 4127 "Invert": "0", 4128 "AnyThread": "1", 4129 "EdgeDetect": "0", 4130 "PEBS": "0", 4131 "Offcore": "0" 4132 }, 4133 { 4134 "EventCode": "0xB1", 4135 "UMask": "0x3F", 4136 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", 4137 "BriefDescription": "Uops executed on any port (core count)", 4138 "PublicDescription": "Uops executed on any port (core count)", 4139 "Counter": "0,1,2,3", 4140 "SampleAfterValue": "2000000", 4141 "MSRIndex": "0", 4142 "MSRValue": "0", 4143 "CounterMask": "1", 4144 "Invert": "1", 4145 "AnyThread": "1", 4146 "EdgeDetect": "1", 4147 "PEBS": "0", 4148 "Offcore": "0" 4149 }, 4150 { 4151 "EventCode": "0xB1", 4152 "UMask": "0x1F", 4153 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", 4154 "BriefDescription": "Uops executed on ports 0-4 (core count)", 4155 "PublicDescription": "Uops executed on ports 0-4 (core count)", 4156 "Counter": "0,1,2,3", 4157 "SampleAfterValue": "2000000", 4158 "MSRIndex": "0", 4159 "MSRValue": "0", 4160 "CounterMask": "1", 4161 "Invert": "1", 4162 "AnyThread": "1", 4163 "EdgeDetect": "1", 4164 "PEBS": "0", 4165 "Offcore": "0" 4166 }, 4167 { 4168 "EventCode": "0xB1", 4169 "UMask": "0x3F", 4170 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", 4171 "BriefDescription": "Cycles no Uops issued on any port (core count)", 4172 "PublicDescription": "Cycles no Uops issued on any port (core count)", 4173 "Counter": "0,1,2,3", 4174 "SampleAfterValue": "2000000", 4175 "MSRIndex": "0", 4176 "MSRValue": "0", 4177 "CounterMask": "1", 4178 "Invert": "1", 4179 "AnyThread": "1", 4180 "EdgeDetect": "0", 4181 "PEBS": "0", 4182 "Offcore": "0" 4183 }, 4184 { 4185 "EventCode": "0xB1", 4186 "UMask": "0x1F", 4187 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", 4188 "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", 4189 "PublicDescription": "Cycles no Uops issued on ports 0-4 (core count)", 4190 "Counter": "0,1,2,3", 4191 "SampleAfterValue": "2000000", 4192 "MSRIndex": "0", 4193 "MSRValue": "0", 4194 "CounterMask": "1", 4195 "Invert": "1", 4196 "AnyThread": "1", 4197 "EdgeDetect": "0", 4198 "PEBS": "0", 4199 "Offcore": "0" 4200 }, 4201 { 4202 "EventCode": "0xB1", 4203 "UMask": "0x1", 4204 "EventName": "UOPS_EXECUTED.PORT0", 4205 "BriefDescription": "Uops executed on port 0", 4206 "PublicDescription": "Uops executed on port 0", 4207 "Counter": "0,1,2,3", 4208 "SampleAfterValue": "2000000", 4209 "MSRIndex": "0", 4210 "MSRValue": "0", 4211 "CounterMask": "0", 4212 "Invert": "0", 4213 "AnyThread": "0", 4214 "EdgeDetect": "0", 4215 "PEBS": "0", 4216 "Offcore": "0" 4217 }, 4218 { 4219 "EventCode": "0xB1", 4220 "UMask": "0x40", 4221 "EventName": "UOPS_EXECUTED.PORT015", 4222 "BriefDescription": "Uops issued on ports 0, 1 or 5", 4223 "PublicDescription": "Uops issued on ports 0, 1 or 5", 4224 "Counter": "0,1,2,3", 4225 "SampleAfterValue": "2000000", 4226 "MSRIndex": "0", 4227 "MSRValue": "0", 4228 "CounterMask": "0", 4229 "Invert": "0", 4230 "AnyThread": "0", 4231 "EdgeDetect": "0", 4232 "PEBS": "0", 4233 "Offcore": "0" 4234 }, 4235 { 4236 "EventCode": "0xB1", 4237 "UMask": "0x40", 4238 "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", 4239 "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", 4240 "PublicDescription": "Cycles no Uops issued on ports 0, 1 or 5", 4241 "Counter": "0,1,2,3", 4242 "SampleAfterValue": "2000000", 4243 "MSRIndex": "0", 4244 "MSRValue": "0", 4245 "CounterMask": "1", 4246 "Invert": "1", 4247 "AnyThread": "0", 4248 "EdgeDetect": "0", 4249 "PEBS": "0", 4250 "Offcore": "0" 4251 }, 4252 { 4253 "EventCode": "0xB1", 4254 "UMask": "0x2", 4255 "EventName": "UOPS_EXECUTED.PORT1", 4256 "BriefDescription": "Uops executed on port 1", 4257 "PublicDescription": "Uops executed on port 1", 4258 "Counter": "0,1,2,3", 4259 "SampleAfterValue": "2000000", 4260 "MSRIndex": "0", 4261 "MSRValue": "0", 4262 "CounterMask": "0", 4263 "Invert": "0", 4264 "AnyThread": "0", 4265 "EdgeDetect": "0", 4266 "PEBS": "0", 4267 "Offcore": "0" 4268 }, 4269 { 4270 "EventCode": "0xB1", 4271 "UMask": "0x4", 4272 "EventName": "UOPS_EXECUTED.PORT2_CORE", 4273 "BriefDescription": "Uops executed on port 2 (core count)", 4274 "PublicDescription": "Uops executed on port 2 (core count)", 4275 "Counter": "0,1,2,3", 4276 "SampleAfterValue": "2000000", 4277 "MSRIndex": "0", 4278 "MSRValue": "0", 4279 "CounterMask": "0", 4280 "Invert": "0", 4281 "AnyThread": "1", 4282 "EdgeDetect": "0", 4283 "PEBS": "0", 4284 "Offcore": "0" 4285 }, 4286 { 4287 "EventCode": "0xB1", 4288 "UMask": "0x80", 4289 "EventName": "UOPS_EXECUTED.PORT234_CORE", 4290 "BriefDescription": "Uops issued on ports 2, 3 or 4", 4291 "PublicDescription": "Uops issued on ports 2, 3 or 4", 4292 "Counter": "0,1,2,3", 4293 "SampleAfterValue": "2000000", 4294 "MSRIndex": "0", 4295 "MSRValue": "0", 4296 "CounterMask": "0", 4297 "Invert": "0", 4298 "AnyThread": "1", 4299 "EdgeDetect": "0", 4300 "PEBS": "0", 4301 "Offcore": "0" 4302 }, 4303 { 4304 "EventCode": "0xB1", 4305 "UMask": "0x8", 4306 "EventName": "UOPS_EXECUTED.PORT3_CORE", 4307 "BriefDescription": "Uops executed on port 3 (core count)", 4308 "PublicDescription": "Uops executed on port 3 (core count)", 4309 "Counter": "0,1,2,3", 4310 "SampleAfterValue": "2000000", 4311 "MSRIndex": "0", 4312 "MSRValue": "0", 4313 "CounterMask": "0", 4314 "Invert": "0", 4315 "AnyThread": "1", 4316 "EdgeDetect": "0", 4317 "PEBS": "0", 4318 "Offcore": "0" 4319 }, 4320 { 4321 "EventCode": "0xB1", 4322 "UMask": "0x10", 4323 "EventName": "UOPS_EXECUTED.PORT4_CORE", 4324 "BriefDescription": "Uops executed on port 4 (core count)", 4325 "PublicDescription": "Uops executed on port 4 (core count)", 4326 "Counter": "0,1,2,3", 4327 "SampleAfterValue": "2000000", 4328 "MSRIndex": "0", 4329 "MSRValue": "0", 4330 "CounterMask": "0", 4331 "Invert": "0", 4332 "AnyThread": "1", 4333 "EdgeDetect": "0", 4334 "PEBS": "0", 4335 "Offcore": "0" 4336 }, 4337 { 4338 "EventCode": "0xB1", 4339 "UMask": "0x20", 4340 "EventName": "UOPS_EXECUTED.PORT5", 4341 "BriefDescription": "Uops executed on port 5", 4342 "PublicDescription": "Uops executed on port 5", 4343 "Counter": "0,1,2,3", 4344 "SampleAfterValue": "2000000", 4345 "MSRIndex": "0", 4346 "MSRValue": "0", 4347 "CounterMask": "0", 4348 "Invert": "0", 4349 "AnyThread": "0", 4350 "EdgeDetect": "0", 4351 "PEBS": "0", 4352 "Offcore": "0" 4353 }, 4354 { 4355 "EventCode": "0xE", 4356 "UMask": "0x1", 4357 "EventName": "UOPS_ISSUED.ANY", 4358 "BriefDescription": "Uops issued", 4359 "PublicDescription": "Uops issued", 4360 "Counter": "0,1,2,3", 4361 "SampleAfterValue": "2000000", 4362 "MSRIndex": "0", 4363 "MSRValue": "0", 4364 "CounterMask": "0", 4365 "Invert": "0", 4366 "AnyThread": "0", 4367 "EdgeDetect": "0", 4368 "PEBS": "0", 4369 "Offcore": "0" 4370 }, 4371 { 4372 "EventCode": "0xE", 4373 "UMask": "0x1", 4374 "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", 4375 "BriefDescription": "Cycles no Uops were issued on any thread", 4376 "PublicDescription": "Cycles no Uops were issued on any thread", 4377 "Counter": "0,1,2,3", 4378 "SampleAfterValue": "2000000", 4379 "MSRIndex": "0", 4380 "MSRValue": "0", 4381 "CounterMask": "1", 4382 "Invert": "1", 4383 "AnyThread": "1", 4384 "EdgeDetect": "0", 4385 "PEBS": "0", 4386 "Offcore": "0" 4387 }, 4388 { 4389 "EventCode": "0xE", 4390 "UMask": "0x1", 4391 "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", 4392 "BriefDescription": "Cycles Uops were issued on either thread", 4393 "PublicDescription": "Cycles Uops were issued on either thread", 4394 "Counter": "0,1,2,3", 4395 "SampleAfterValue": "2000000", 4396 "MSRIndex": "0", 4397 "MSRValue": "0", 4398 "CounterMask": "1", 4399 "Invert": "0", 4400 "AnyThread": "1", 4401 "EdgeDetect": "0", 4402 "PEBS": "0", 4403 "Offcore": "0" 4404 }, 4405 { 4406 "EventCode": "0xE", 4407 "UMask": "0x2", 4408 "EventName": "UOPS_ISSUED.FUSED", 4409 "BriefDescription": "Fused Uops issued", 4410 "PublicDescription": "Fused Uops issued", 4411 "Counter": "0,1,2,3", 4412 "SampleAfterValue": "2000000", 4413 "MSRIndex": "0", 4414 "MSRValue": "0", 4415 "CounterMask": "0", 4416 "Invert": "0", 4417 "AnyThread": "0", 4418 "EdgeDetect": "0", 4419 "PEBS": "0", 4420 "Offcore": "0" 4421 }, 4422 { 4423 "EventCode": "0xE", 4424 "UMask": "0x1", 4425 "EventName": "UOPS_ISSUED.STALL_CYCLES", 4426 "BriefDescription": "Cycles no Uops were issued", 4427 "PublicDescription": "Cycles no Uops were issued", 4428 "Counter": "0,1,2,3", 4429 "SampleAfterValue": "2000000", 4430 "MSRIndex": "0", 4431 "MSRValue": "0", 4432 "CounterMask": "1", 4433 "Invert": "1", 4434 "AnyThread": "0", 4435 "EdgeDetect": "0", 4436 "PEBS": "0", 4437 "Offcore": "0" 4438 }, 4439 { 4440 "EventCode": "0xC2", 4441 "UMask": "0x1", 4442 "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", 4443 "BriefDescription": "Cycles Uops are being retired", 4444 "PublicDescription": "Cycles Uops are being retired", 4445 "Counter": "0,1,2,3", 4446 "SampleAfterValue": "2000000", 4447 "MSRIndex": "0", 4448 "MSRValue": "0", 4449 "CounterMask": "1", 4450 "Invert": "0", 4451 "AnyThread": "0", 4452 "EdgeDetect": "0", 4453 "PEBS": "1", 4454 "Offcore": "0" 4455 }, 4456 { 4457 "EventCode": "0xC2", 4458 "UMask": "0x1", 4459 "EventName": "UOPS_RETIRED.ANY", 4460 "BriefDescription": "Uops retired (Precise Event)", 4461 "PublicDescription": "Uops retired (Precise Event)", 4462 "Counter": "0,1,2,3", 4463 "SampleAfterValue": "2000000", 4464 "MSRIndex": "0", 4465 "MSRValue": "0", 4466 "CounterMask": "0", 4467 "Invert": "0", 4468 "AnyThread": "0", 4469 "EdgeDetect": "0", 4470 "PEBS": "1", 4471 "Offcore": "0" 4472 }, 4473 { 4474 "EventCode": "0xC2", 4475 "UMask": "0x4", 4476 "EventName": "UOPS_RETIRED.MACRO_FUSED", 4477 "BriefDescription": "Macro-fused Uops retired (Precise Event)", 4478 "PublicDescription": "Macro-fused Uops retired (Precise Event)", 4479 "Counter": "0,1,2,3", 4480 "SampleAfterValue": "2000000", 4481 "MSRIndex": "0", 4482 "MSRValue": "0", 4483 "CounterMask": "0", 4484 "Invert": "0", 4485 "AnyThread": "0", 4486 "EdgeDetect": "0", 4487 "PEBS": "1", 4488 "Offcore": "0" 4489 }, 4490 { 4491 "EventCode": "0xC2", 4492 "UMask": "0x2", 4493 "EventName": "UOPS_RETIRED.RETIRE_SLOTS", 4494 "BriefDescription": "Retirement slots used (Precise Event)", 4495 "PublicDescription": "Retirement slots used (Precise Event)", 4496 "Counter": "0,1,2,3", 4497 "SampleAfterValue": "2000000", 4498 "MSRIndex": "0", 4499 "MSRValue": "0", 4500 "CounterMask": "0", 4501 "Invert": "0", 4502 "AnyThread": "0", 4503 "EdgeDetect": "0", 4504 "PEBS": "1", 4505 "Offcore": "0" 4506 }, 4507 { 4508 "EventCode": "0xC2", 4509 "UMask": "0x1", 4510 "EventName": "UOPS_RETIRED.STALL_CYCLES", 4511 "BriefDescription": "Cycles Uops are not retiring (Precise Event)", 4512 "PublicDescription": "Cycles Uops are not retiring (Precise Event)", 4513 "Counter": "0,1,2,3", 4514 "SampleAfterValue": "2000000", 4515 "MSRIndex": "0", 4516 "MSRValue": "0", 4517 "CounterMask": "1", 4518 "Invert": "1", 4519 "AnyThread": "0", 4520 "EdgeDetect": "0", 4521 "PEBS": "1", 4522 "Offcore": "0" 4523 }, 4524 { 4525 "EventCode": "0xC2", 4526 "UMask": "0x1", 4527 "EventName": "UOPS_RETIRED.TOTAL_CYCLES", 4528 "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", 4529 "PublicDescription": "Total cycles using precise uop retired event (Precise Event)", 4530 "Counter": "0,1,2,3", 4531 "SampleAfterValue": "2000000", 4532 "MSRIndex": "0", 4533 "MSRValue": "0", 4534 "CounterMask": "16", 4535 "Invert": "1", 4536 "AnyThread": "0", 4537 "EdgeDetect": "0", 4538 "PEBS": "1", 4539 "Offcore": "0" 4540 }, 4541 { 4542 "EventCode": "0xC0", 4543 "UMask": "0x1", 4544 "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", 4545 "BriefDescription": "Total cycles (Precise Event)", 4546 "PublicDescription": "Total cycles (Precise Event)", 4547 "Counter": "0,1,2,3", 4548 "SampleAfterValue": "2000000", 4549 "MSRIndex": "0", 4550 "MSRValue": "0", 4551 "CounterMask": "16", 4552 "Invert": "1", 4553 "AnyThread": "0", 4554 "EdgeDetect": "0", 4555 "PEBS": "2", 4556 "Offcore": "0" 4557 }, 4558 { 4559 "EventCode": "0xB", 4560 "UMask": "0x10", 4561 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 4562 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 4563 "PublicDescription": "Memory instructions retired above 0 clocks (Precise Event)", 4564 "Counter": "3", 4565 "SampleAfterValue": "2000000", 4566 "MSRIndex": "0x3F6", 4567 "MSRValue": "0x0", 4568 "CounterMask": "0", 4569 "Invert": "0", 4570 "AnyThread": "0", 4571 "EdgeDetect": "0", 4572 "PEBS": "2", 4573 "Offcore": "0" 4574 }, 4575 { 4576 "EventCode": "0xB", 4577 "UMask": "0x10", 4578 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 4579 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 4580 "PublicDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 4581 "Counter": "3", 4582 "SampleAfterValue": "100", 4583 "MSRIndex": "0x3F6", 4584 "MSRValue": "0x400", 4585 "CounterMask": "0", 4586 "Invert": "0", 4587 "AnyThread": "0", 4588 "EdgeDetect": "0", 4589 "PEBS": "2", 4590 "Offcore": "0" 4591 }, 4592 { 4593 "EventCode": "0xB", 4594 "UMask": "0x10", 4595 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 4596 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 4597 "PublicDescription": "Memory instructions retired above 128 clocks (Precise Event)", 4598 "Counter": "3", 4599 "SampleAfterValue": "1000", 4600 "MSRIndex": "0x3F6", 4601 "MSRValue": "0x80", 4602 "CounterMask": "0", 4603 "Invert": "0", 4604 "AnyThread": "0", 4605 "EdgeDetect": "0", 4606 "PEBS": "2", 4607 "Offcore": "0" 4608 }, 4609 { 4610 "EventCode": "0xB", 4611 "UMask": "0x10", 4612 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 4613 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 4614 "PublicDescription": "Memory instructions retired above 16 clocks (Precise Event)", 4615 "Counter": "3", 4616 "SampleAfterValue": "10000", 4617 "MSRIndex": "0x3F6", 4618 "MSRValue": "0x10", 4619 "CounterMask": "0", 4620 "Invert": "0", 4621 "AnyThread": "0", 4622 "EdgeDetect": "0", 4623 "PEBS": "2", 4624 "Offcore": "0" 4625 }, 4626 { 4627 "EventCode": "0xB", 4628 "UMask": "0x10", 4629 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 4630 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 4631 "PublicDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 4632 "Counter": "3", 4633 "SampleAfterValue": "5", 4634 "MSRIndex": "0x3F6", 4635 "MSRValue": "0x4000", 4636 "CounterMask": "0", 4637 "Invert": "0", 4638 "AnyThread": "0", 4639 "EdgeDetect": "0", 4640 "PEBS": "2", 4641 "Offcore": "0" 4642 }, 4643 { 4644 "EventCode": "0xB", 4645 "UMask": "0x10", 4646 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 4647 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 4648 "PublicDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 4649 "Counter": "3", 4650 "SampleAfterValue": "50", 4651 "MSRIndex": "0x3F6", 4652 "MSRValue": "0x800", 4653 "CounterMask": "0", 4654 "Invert": "0", 4655 "AnyThread": "0", 4656 "EdgeDetect": "0", 4657 "PEBS": "2", 4658 "Offcore": "0" 4659 }, 4660 { 4661 "EventCode": "0xB", 4662 "UMask": "0x10", 4663 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 4664 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 4665 "PublicDescription": "Memory instructions retired above 256 clocks (Precise Event)", 4666 "Counter": "3", 4667 "SampleAfterValue": "500", 4668 "MSRIndex": "0x3F6", 4669 "MSRValue": "0x100", 4670 "CounterMask": "0", 4671 "Invert": "0", 4672 "AnyThread": "0", 4673 "EdgeDetect": "0", 4674 "PEBS": "2", 4675 "Offcore": "0" 4676 }, 4677 { 4678 "EventCode": "0xB", 4679 "UMask": "0x10", 4680 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 4681 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 4682 "PublicDescription": "Memory instructions retired above 32 clocks (Precise Event)", 4683 "Counter": "3", 4684 "SampleAfterValue": "5000", 4685 "MSRIndex": "0x3F6", 4686 "MSRValue": "0x20", 4687 "CounterMask": "0", 4688 "Invert": "0", 4689 "AnyThread": "0", 4690 "EdgeDetect": "0", 4691 "PEBS": "2", 4692 "Offcore": "0" 4693 }, 4694 { 4695 "EventCode": "0xB", 4696 "UMask": "0x10", 4697 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 4698 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 4699 "PublicDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 4700 "Counter": "3", 4701 "SampleAfterValue": "3", 4702 "MSRIndex": "0x3F6", 4703 "MSRValue": "0x8000", 4704 "CounterMask": "0", 4705 "Invert": "0", 4706 "AnyThread": "0", 4707 "EdgeDetect": "0", 4708 "PEBS": "2", 4709 "Offcore": "0" 4710 }, 4711 { 4712 "EventCode": "0xB", 4713 "UMask": "0x10", 4714 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 4715 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 4716 "PublicDescription": "Memory instructions retired above 4 clocks (Precise Event)", 4717 "Counter": "3", 4718 "SampleAfterValue": "50000", 4719 "MSRIndex": "0x3F6", 4720 "MSRValue": "0x4", 4721 "CounterMask": "0", 4722 "Invert": "0", 4723 "AnyThread": "0", 4724 "EdgeDetect": "0", 4725 "PEBS": "2", 4726 "Offcore": "0" 4727 }, 4728 { 4729 "EventCode": "0xB", 4730 "UMask": "0x10", 4731 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 4732 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 4733 "PublicDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 4734 "Counter": "3", 4735 "SampleAfterValue": "20", 4736 "MSRIndex": "0x3F6", 4737 "MSRValue": "0x1000", 4738 "CounterMask": "0", 4739 "Invert": "0", 4740 "AnyThread": "0", 4741 "EdgeDetect": "0", 4742 "PEBS": "2", 4743 "Offcore": "0" 4744 }, 4745 { 4746 "EventCode": "0xB", 4747 "UMask": "0x10", 4748 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 4749 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 4750 "PublicDescription": "Memory instructions retired above 512 clocks (Precise Event)", 4751 "Counter": "3", 4752 "SampleAfterValue": "200", 4753 "MSRIndex": "0x3F6", 4754 "MSRValue": "0x200", 4755 "CounterMask": "0", 4756 "Invert": "0", 4757 "AnyThread": "0", 4758 "EdgeDetect": "0", 4759 "PEBS": "2", 4760 "Offcore": "0" 4761 }, 4762 { 4763 "EventCode": "0xB", 4764 "UMask": "0x10", 4765 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 4766 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 4767 "PublicDescription": "Memory instructions retired above 64 clocks (Precise Event)", 4768 "Counter": "3", 4769 "SampleAfterValue": "2000", 4770 "MSRIndex": "0x3F6", 4771 "MSRValue": "0x40", 4772 "CounterMask": "0", 4773 "Invert": "0", 4774 "AnyThread": "0", 4775 "EdgeDetect": "0", 4776 "PEBS": "2", 4777 "Offcore": "0" 4778 }, 4779 { 4780 "EventCode": "0xB", 4781 "UMask": "0x10", 4782 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 4783 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 4784 "PublicDescription": "Memory instructions retired above 8 clocks (Precise Event)", 4785 "Counter": "3", 4786 "SampleAfterValue": "20000", 4787 "MSRIndex": "0x3F6", 4788 "MSRValue": "0x8", 4789 "CounterMask": "0", 4790 "Invert": "0", 4791 "AnyThread": "0", 4792 "EdgeDetect": "0", 4793 "PEBS": "2", 4794 "Offcore": "0" 4795 }, 4796 { 4797 "EventCode": "0xB", 4798 "UMask": "0x10", 4799 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 4800 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 4801 "PublicDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 4802 "Counter": "3", 4803 "SampleAfterValue": "10", 4804 "MSRIndex": "0x3F6", 4805 "MSRValue": "0x2000", 4806 "CounterMask": "0", 4807 "Invert": "0", 4808 "AnyThread": "0", 4809 "EdgeDetect": "0", 4810 "PEBS": "2", 4811 "Offcore": "0" 4812 } 4813, 4814 { 4815 "EventCode": "0xB7", 4816 "UMask": "0x1", 4817 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM", 4818 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 4819 "PublicDescription": "Offcore data reads satisfied by any cache or DRAM", 4820 "Counter": "2", 4821 "SampleAfterValue": "100000", 4822 "MSRIndex": "0x1A6", 4823 "MSRValue": "0x7F11", 4824 "CounterMask": "0", 4825 "Invert": "0", 4826 "AnyThread": "0", 4827 "EdgeDetect": "0", 4828 "PEBS": "0", 4829 "Offcore": "1" 4830 }, 4831 { 4832 "EventCode": "0xB7", 4833 "UMask": "0x1", 4834 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM", 4835 "BriefDescription": "Offcore data reads satisfied by any DRAM", 4836 "PublicDescription": "Offcore data reads satisfied by any DRAM", 4837 "Counter": "2", 4838 "SampleAfterValue": "100000", 4839 "MSRIndex": "0x1A6", 4840 "MSRValue": "0x6011", 4841 "CounterMask": "0", 4842 "Invert": "0", 4843 "AnyThread": "0", 4844 "EdgeDetect": "0", 4845 "PEBS": "0", 4846 "Offcore": "1" 4847 }, 4848 { 4849 "EventCode": "0xB7", 4850 "UMask": "0x1", 4851 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS", 4852 "BriefDescription": "Offcore data reads that missed the LLC", 4853 "PublicDescription": "Offcore data reads that missed the LLC", 4854 "Counter": "2", 4855 "SampleAfterValue": "100000", 4856 "MSRIndex": "0x1A6", 4857 "MSRValue": "0xF811", 4858 "CounterMask": "0", 4859 "Invert": "0", 4860 "AnyThread": "0", 4861 "EdgeDetect": "0", 4862 "PEBS": "0", 4863 "Offcore": "1" 4864 }, 4865 { 4866 "EventCode": "0xB7", 4867 "UMask": "0x1", 4868 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION", 4869 "BriefDescription": "All offcore data reads", 4870 "PublicDescription": "All offcore data reads", 4871 "Counter": "2", 4872 "SampleAfterValue": "100000", 4873 "MSRIndex": "0x1A6", 4874 "MSRValue": "0xFF11", 4875 "CounterMask": "0", 4876 "Invert": "0", 4877 "AnyThread": "0", 4878 "EdgeDetect": "0", 4879 "PEBS": "0", 4880 "Offcore": "1" 4881 }, 4882 { 4883 "EventCode": "0xB7", 4884 "UMask": "0x1", 4885 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO", 4886 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 4887 "PublicDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 4888 "Counter": "2", 4889 "SampleAfterValue": "100000", 4890 "MSRIndex": "0x1A6", 4891 "MSRValue": "0x8011", 4892 "CounterMask": "0", 4893 "Invert": "0", 4894 "AnyThread": "0", 4895 "EdgeDetect": "0", 4896 "PEBS": "0", 4897 "Offcore": "1" 4898 }, 4899 { 4900 "EventCode": "0xB7", 4901 "UMask": "0x1", 4902 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 4903 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 4904 "PublicDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 4905 "Counter": "2", 4906 "SampleAfterValue": "100000", 4907 "MSRIndex": "0x1A6", 4908 "MSRValue": "0x111", 4909 "CounterMask": "0", 4910 "Invert": "0", 4911 "AnyThread": "0", 4912 "EdgeDetect": "0", 4913 "PEBS": "0", 4914 "Offcore": "1" 4915 }, 4916 { 4917 "EventCode": "0xB7", 4918 "UMask": "0x1", 4919 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 4920 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 4921 "PublicDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 4922 "Counter": "2", 4923 "SampleAfterValue": "100000", 4924 "MSRIndex": "0x1A6", 4925 "MSRValue": "0x211", 4926 "CounterMask": "0", 4927 "Invert": "0", 4928 "AnyThread": "0", 4929 "EdgeDetect": "0", 4930 "PEBS": "0", 4931 "Offcore": "1" 4932 }, 4933 { 4934 "EventCode": "0xB7", 4935 "UMask": "0x1", 4936 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 4937 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 4938 "PublicDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 4939 "Counter": "2", 4940 "SampleAfterValue": "100000", 4941 "MSRIndex": "0x1A6", 4942 "MSRValue": "0x411", 4943 "CounterMask": "0", 4944 "Invert": "0", 4945 "AnyThread": "0", 4946 "EdgeDetect": "0", 4947 "PEBS": "0", 4948 "Offcore": "1" 4949 }, 4950 { 4951 "EventCode": "0xB7", 4952 "UMask": "0x1", 4953 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE", 4954 "BriefDescription": "Offcore data reads satisfied by the LLC", 4955 "PublicDescription": "Offcore data reads satisfied by the LLC", 4956 "Counter": "2", 4957 "SampleAfterValue": "100000", 4958 "MSRIndex": "0x1A6", 4959 "MSRValue": "0x711", 4960 "CounterMask": "0", 4961 "Invert": "0", 4962 "AnyThread": "0", 4963 "EdgeDetect": "0", 4964 "PEBS": "0", 4965 "Offcore": "1" 4966 }, 4967 { 4968 "EventCode": "0xB7", 4969 "UMask": "0x1", 4970 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM", 4971 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 4972 "PublicDescription": "Offcore data reads satisfied by the LLC or local DRAM", 4973 "Counter": "2", 4974 "SampleAfterValue": "100000", 4975 "MSRIndex": "0x1A6", 4976 "MSRValue": "0x4711", 4977 "CounterMask": "0", 4978 "Invert": "0", 4979 "AnyThread": "0", 4980 "EdgeDetect": "0", 4981 "PEBS": "0", 4982 "Offcore": "1" 4983 }, 4984 { 4985 "EventCode": "0xB7", 4986 "UMask": "0x1", 4987 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM", 4988 "BriefDescription": "Offcore data reads satisfied by the local DRAM", 4989 "PublicDescription": "Offcore data reads satisfied by the local DRAM", 4990 "Counter": "2", 4991 "SampleAfterValue": "100000", 4992 "MSRIndex": "0x1A6", 4993 "MSRValue": "0x4011", 4994 "CounterMask": "0", 4995 "Invert": "0", 4996 "AnyThread": "0", 4997 "EdgeDetect": "0", 4998 "PEBS": "0", 4999 "Offcore": "1" 5000 }, 5001 { 5002 "EventCode": "0xB7", 5003 "UMask": "0x1", 5004 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE", 5005 "BriefDescription": "Offcore data reads satisfied by a remote cache", 5006 "PublicDescription": "Offcore data reads satisfied by a remote cache", 5007 "Counter": "2", 5008 "SampleAfterValue": "100000", 5009 "MSRIndex": "0x1A6", 5010 "MSRValue": "0x1811", 5011 "CounterMask": "0", 5012 "Invert": "0", 5013 "AnyThread": "0", 5014 "EdgeDetect": "0", 5015 "PEBS": "0", 5016 "Offcore": "1" 5017 }, 5018 { 5019 "EventCode": "0xB7", 5020 "UMask": "0x1", 5021 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM", 5022 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 5023 "PublicDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 5024 "Counter": "2", 5025 "SampleAfterValue": "100000", 5026 "MSRIndex": "0x1A6", 5027 "MSRValue": "0x3811", 5028 "CounterMask": "0", 5029 "Invert": "0", 5030 "AnyThread": "0", 5031 "EdgeDetect": "0", 5032 "PEBS": "0", 5033 "Offcore": "1" 5034 }, 5035 { 5036 "EventCode": "0xB7", 5037 "UMask": "0x1", 5038 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT", 5039 "BriefDescription": "Offcore data reads that HIT in a remote cache", 5040 "PublicDescription": "Offcore data reads that HIT in a remote cache", 5041 "Counter": "2", 5042 "SampleAfterValue": "100000", 5043 "MSRIndex": "0x1A6", 5044 "MSRValue": "0x1011", 5045 "CounterMask": "0", 5046 "Invert": "0", 5047 "AnyThread": "0", 5048 "EdgeDetect": "0", 5049 "PEBS": "0", 5050 "Offcore": "1" 5051 }, 5052 { 5053 "EventCode": "0xB7", 5054 "UMask": "0x1", 5055 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM", 5056 "BriefDescription": "Offcore data reads that HITM in a remote cache", 5057 "PublicDescription": "Offcore data reads that HITM in a remote cache", 5058 "Counter": "2", 5059 "SampleAfterValue": "100000", 5060 "MSRIndex": "0x1A6", 5061 "MSRValue": "0x811", 5062 "CounterMask": "0", 5063 "Invert": "0", 5064 "AnyThread": "0", 5065 "EdgeDetect": "0", 5066 "PEBS": "0", 5067 "Offcore": "1" 5068 }, 5069 { 5070 "EventCode": "0xB7", 5071 "UMask": "0x1", 5072 "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM", 5073 "BriefDescription": "Offcore data reads satisfied by a remote DRAM", 5074 "PublicDescription": "Offcore data reads satisfied by a remote DRAM", 5075 "Counter": "2", 5076 "SampleAfterValue": "100000", 5077 "MSRIndex": "0x1A6", 5078 "MSRValue": "0x2011", 5079 "CounterMask": "0", 5080 "Invert": "0", 5081 "AnyThread": "0", 5082 "EdgeDetect": "0", 5083 "PEBS": "0", 5084 "Offcore": "1" 5085 }, 5086 { 5087 "EventCode": "0xB7", 5088 "UMask": "0x1", 5089 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM", 5090 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 5091 "PublicDescription": "Offcore code reads satisfied by any cache or DRAM", 5092 "Counter": "2", 5093 "SampleAfterValue": "100000", 5094 "MSRIndex": "0x1A6", 5095 "MSRValue": "0x7F44", 5096 "CounterMask": "0", 5097 "Invert": "0", 5098 "AnyThread": "0", 5099 "EdgeDetect": "0", 5100 "PEBS": "0", 5101 "Offcore": "1" 5102 }, 5103 { 5104 "EventCode": "0xB7", 5105 "UMask": "0x1", 5106 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM", 5107 "BriefDescription": "Offcore code reads satisfied by any DRAM", 5108 "PublicDescription": "Offcore code reads satisfied by any DRAM", 5109 "Counter": "2", 5110 "SampleAfterValue": "100000", 5111 "MSRIndex": "0x1A6", 5112 "MSRValue": "0x6044", 5113 "CounterMask": "0", 5114 "Invert": "0", 5115 "AnyThread": "0", 5116 "EdgeDetect": "0", 5117 "PEBS": "0", 5118 "Offcore": "1" 5119 }, 5120 { 5121 "EventCode": "0xB7", 5122 "UMask": "0x1", 5123 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS", 5124 "BriefDescription": "Offcore code reads that missed the LLC", 5125 "PublicDescription": "Offcore code reads that missed the LLC", 5126 "Counter": "2", 5127 "SampleAfterValue": "100000", 5128 "MSRIndex": "0x1A6", 5129 "MSRValue": "0xF844", 5130 "CounterMask": "0", 5131 "Invert": "0", 5132 "AnyThread": "0", 5133 "EdgeDetect": "0", 5134 "PEBS": "0", 5135 "Offcore": "1" 5136 }, 5137 { 5138 "EventCode": "0xB7", 5139 "UMask": "0x1", 5140 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION", 5141 "BriefDescription": "All offcore code reads", 5142 "PublicDescription": "All offcore code reads", 5143 "Counter": "2", 5144 "SampleAfterValue": "100000", 5145 "MSRIndex": "0x1A6", 5146 "MSRValue": "0xFF44", 5147 "CounterMask": "0", 5148 "Invert": "0", 5149 "AnyThread": "0", 5150 "EdgeDetect": "0", 5151 "PEBS": "0", 5152 "Offcore": "1" 5153 }, 5154 { 5155 "EventCode": "0xB7", 5156 "UMask": "0x1", 5157 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO", 5158 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 5159 "PublicDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 5160 "Counter": "2", 5161 "SampleAfterValue": "100000", 5162 "MSRIndex": "0x1A6", 5163 "MSRValue": "0x8044", 5164 "CounterMask": "0", 5165 "Invert": "0", 5166 "AnyThread": "0", 5167 "EdgeDetect": "0", 5168 "PEBS": "0", 5169 "Offcore": "1" 5170 }, 5171 { 5172 "EventCode": "0xB7", 5173 "UMask": "0x1", 5174 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 5175 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 5176 "PublicDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 5177 "Counter": "2", 5178 "SampleAfterValue": "100000", 5179 "MSRIndex": "0x1A6", 5180 "MSRValue": "0x144", 5181 "CounterMask": "0", 5182 "Invert": "0", 5183 "AnyThread": "0", 5184 "EdgeDetect": "0", 5185 "PEBS": "0", 5186 "Offcore": "1" 5187 }, 5188 { 5189 "EventCode": "0xB7", 5190 "UMask": "0x1", 5191 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 5192 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 5193 "PublicDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 5194 "Counter": "2", 5195 "SampleAfterValue": "100000", 5196 "MSRIndex": "0x1A6", 5197 "MSRValue": "0x244", 5198 "CounterMask": "0", 5199 "Invert": "0", 5200 "AnyThread": "0", 5201 "EdgeDetect": "0", 5202 "PEBS": "0", 5203 "Offcore": "1" 5204 }, 5205 { 5206 "EventCode": "0xB7", 5207 "UMask": "0x1", 5208 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 5209 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 5210 "PublicDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 5211 "Counter": "2", 5212 "SampleAfterValue": "100000", 5213 "MSRIndex": "0x1A6", 5214 "MSRValue": "0x444", 5215 "CounterMask": "0", 5216 "Invert": "0", 5217 "AnyThread": "0", 5218 "EdgeDetect": "0", 5219 "PEBS": "0", 5220 "Offcore": "1" 5221 }, 5222 { 5223 "EventCode": "0xB7", 5224 "UMask": "0x1", 5225 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE", 5226 "BriefDescription": "Offcore code reads satisfied by the LLC", 5227 "PublicDescription": "Offcore code reads satisfied by the LLC", 5228 "Counter": "2", 5229 "SampleAfterValue": "100000", 5230 "MSRIndex": "0x1A6", 5231 "MSRValue": "0x744", 5232 "CounterMask": "0", 5233 "Invert": "0", 5234 "AnyThread": "0", 5235 "EdgeDetect": "0", 5236 "PEBS": "0", 5237 "Offcore": "1" 5238 }, 5239 { 5240 "EventCode": "0xB7", 5241 "UMask": "0x1", 5242 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM", 5243 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 5244 "PublicDescription": "Offcore code reads satisfied by the LLC or local DRAM", 5245 "Counter": "2", 5246 "SampleAfterValue": "100000", 5247 "MSRIndex": "0x1A6", 5248 "MSRValue": "0x4744", 5249 "CounterMask": "0", 5250 "Invert": "0", 5251 "AnyThread": "0", 5252 "EdgeDetect": "0", 5253 "PEBS": "0", 5254 "Offcore": "1" 5255 }, 5256 { 5257 "EventCode": "0xB7", 5258 "UMask": "0x1", 5259 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM", 5260 "BriefDescription": "Offcore code reads satisfied by the local DRAM", 5261 "PublicDescription": "Offcore code reads satisfied by the local DRAM", 5262 "Counter": "2", 5263 "SampleAfterValue": "100000", 5264 "MSRIndex": "0x1A6", 5265 "MSRValue": "0x4044", 5266 "CounterMask": "0", 5267 "Invert": "0", 5268 "AnyThread": "0", 5269 "EdgeDetect": "0", 5270 "PEBS": "0", 5271 "Offcore": "1" 5272 }, 5273 { 5274 "EventCode": "0xB7", 5275 "UMask": "0x1", 5276 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE", 5277 "BriefDescription": "Offcore code reads satisfied by a remote cache", 5278 "PublicDescription": "Offcore code reads satisfied by a remote cache", 5279 "Counter": "2", 5280 "SampleAfterValue": "100000", 5281 "MSRIndex": "0x1A6", 5282 "MSRValue": "0x1844", 5283 "CounterMask": "0", 5284 "Invert": "0", 5285 "AnyThread": "0", 5286 "EdgeDetect": "0", 5287 "PEBS": "0", 5288 "Offcore": "1" 5289 }, 5290 { 5291 "EventCode": "0xB7", 5292 "UMask": "0x1", 5293 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM", 5294 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 5295 "PublicDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 5296 "Counter": "2", 5297 "SampleAfterValue": "100000", 5298 "MSRIndex": "0x1A6", 5299 "MSRValue": "0x3844", 5300 "CounterMask": "0", 5301 "Invert": "0", 5302 "AnyThread": "0", 5303 "EdgeDetect": "0", 5304 "PEBS": "0", 5305 "Offcore": "1" 5306 }, 5307 { 5308 "EventCode": "0xB7", 5309 "UMask": "0x1", 5310 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT", 5311 "BriefDescription": "Offcore code reads that HIT in a remote cache", 5312 "PublicDescription": "Offcore code reads that HIT in a remote cache", 5313 "Counter": "2", 5314 "SampleAfterValue": "100000", 5315 "MSRIndex": "0x1A6", 5316 "MSRValue": "0x1044", 5317 "CounterMask": "0", 5318 "Invert": "0", 5319 "AnyThread": "0", 5320 "EdgeDetect": "0", 5321 "PEBS": "0", 5322 "Offcore": "1" 5323 }, 5324 { 5325 "EventCode": "0xB7", 5326 "UMask": "0x1", 5327 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM", 5328 "BriefDescription": "Offcore code reads that HITM in a remote cache", 5329 "PublicDescription": "Offcore code reads that HITM in a remote cache", 5330 "Counter": "2", 5331 "SampleAfterValue": "100000", 5332 "MSRIndex": "0x1A6", 5333 "MSRValue": "0x844", 5334 "CounterMask": "0", 5335 "Invert": "0", 5336 "AnyThread": "0", 5337 "EdgeDetect": "0", 5338 "PEBS": "0", 5339 "Offcore": "1" 5340 }, 5341 { 5342 "EventCode": "0xB7", 5343 "UMask": "0x1", 5344 "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM", 5345 "BriefDescription": "Offcore code reads satisfied by a remote DRAM", 5346 "PublicDescription": "Offcore code reads satisfied by a remote DRAM", 5347 "Counter": "2", 5348 "SampleAfterValue": "100000", 5349 "MSRIndex": "0x1A6", 5350 "MSRValue": "0x2044", 5351 "CounterMask": "0", 5352 "Invert": "0", 5353 "AnyThread": "0", 5354 "EdgeDetect": "0", 5355 "PEBS": "0", 5356 "Offcore": "1" 5357 }, 5358 { 5359 "EventCode": "0xB7", 5360 "UMask": "0x1", 5361 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM", 5362 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 5363 "PublicDescription": "Offcore requests satisfied by any cache or DRAM", 5364 "Counter": "2", 5365 "SampleAfterValue": "100000", 5366 "MSRIndex": "0x1A6", 5367 "MSRValue": "0x7FFF", 5368 "CounterMask": "0", 5369 "Invert": "0", 5370 "AnyThread": "0", 5371 "EdgeDetect": "0", 5372 "PEBS": "0", 5373 "Offcore": "1" 5374 }, 5375 { 5376 "EventCode": "0xB7", 5377 "UMask": "0x1", 5378 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM", 5379 "BriefDescription": "Offcore requests satisfied by any DRAM", 5380 "PublicDescription": "Offcore requests satisfied by any DRAM", 5381 "Counter": "2", 5382 "SampleAfterValue": "100000", 5383 "MSRIndex": "0x1A6", 5384 "MSRValue": "0x60FF", 5385 "CounterMask": "0", 5386 "Invert": "0", 5387 "AnyThread": "0", 5388 "EdgeDetect": "0", 5389 "PEBS": "0", 5390 "Offcore": "1" 5391 }, 5392 { 5393 "EventCode": "0xB7", 5394 "UMask": "0x1", 5395 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS", 5396 "BriefDescription": "Offcore requests that missed the LLC", 5397 "PublicDescription": "Offcore requests that missed the LLC", 5398 "Counter": "2", 5399 "SampleAfterValue": "100000", 5400 "MSRIndex": "0x1A6", 5401 "MSRValue": "0xF8FF", 5402 "CounterMask": "0", 5403 "Invert": "0", 5404 "AnyThread": "0", 5405 "EdgeDetect": "0", 5406 "PEBS": "0", 5407 "Offcore": "1" 5408 }, 5409 { 5410 "EventCode": "0xB7", 5411 "UMask": "0x1", 5412 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION", 5413 "BriefDescription": "All offcore requests", 5414 "PublicDescription": "All offcore requests", 5415 "Counter": "2", 5416 "SampleAfterValue": "100000", 5417 "MSRIndex": "0x1A6", 5418 "MSRValue": "0xFFFF", 5419 "CounterMask": "0", 5420 "Invert": "0", 5421 "AnyThread": "0", 5422 "EdgeDetect": "0", 5423 "PEBS": "0", 5424 "Offcore": "1" 5425 }, 5426 { 5427 "EventCode": "0xB7", 5428 "UMask": "0x1", 5429 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO", 5430 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 5431 "PublicDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 5432 "Counter": "2", 5433 "SampleAfterValue": "100000", 5434 "MSRIndex": "0x1A6", 5435 "MSRValue": "0x80FF", 5436 "CounterMask": "0", 5437 "Invert": "0", 5438 "AnyThread": "0", 5439 "EdgeDetect": "0", 5440 "PEBS": "0", 5441 "Offcore": "1" 5442 }, 5443 { 5444 "EventCode": "0xB7", 5445 "UMask": "0x1", 5446 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 5447 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 5448 "PublicDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 5449 "Counter": "2", 5450 "SampleAfterValue": "100000", 5451 "MSRIndex": "0x1A6", 5452 "MSRValue": "0x1FF", 5453 "CounterMask": "0", 5454 "Invert": "0", 5455 "AnyThread": "0", 5456 "EdgeDetect": "0", 5457 "PEBS": "0", 5458 "Offcore": "1" 5459 }, 5460 { 5461 "EventCode": "0xB7", 5462 "UMask": "0x1", 5463 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 5464 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 5465 "PublicDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 5466 "Counter": "2", 5467 "SampleAfterValue": "100000", 5468 "MSRIndex": "0x1A6", 5469 "MSRValue": "0x2FF", 5470 "CounterMask": "0", 5471 "Invert": "0", 5472 "AnyThread": "0", 5473 "EdgeDetect": "0", 5474 "PEBS": "0", 5475 "Offcore": "1" 5476 }, 5477 { 5478 "EventCode": "0xB7", 5479 "UMask": "0x1", 5480 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 5481 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 5482 "PublicDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 5483 "Counter": "2", 5484 "SampleAfterValue": "100000", 5485 "MSRIndex": "0x1A6", 5486 "MSRValue": "0x4FF", 5487 "CounterMask": "0", 5488 "Invert": "0", 5489 "AnyThread": "0", 5490 "EdgeDetect": "0", 5491 "PEBS": "0", 5492 "Offcore": "1" 5493 }, 5494 { 5495 "EventCode": "0xB7", 5496 "UMask": "0x1", 5497 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE", 5498 "BriefDescription": "Offcore requests satisfied by the LLC", 5499 "PublicDescription": "Offcore requests satisfied by the LLC", 5500 "Counter": "2", 5501 "SampleAfterValue": "100000", 5502 "MSRIndex": "0x1A6", 5503 "MSRValue": "0x7FF", 5504 "CounterMask": "0", 5505 "Invert": "0", 5506 "AnyThread": "0", 5507 "EdgeDetect": "0", 5508 "PEBS": "0", 5509 "Offcore": "1" 5510 }, 5511 { 5512 "EventCode": "0xB7", 5513 "UMask": "0x1", 5514 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM", 5515 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 5516 "PublicDescription": "Offcore requests satisfied by the LLC or local DRAM", 5517 "Counter": "2", 5518 "SampleAfterValue": "100000", 5519 "MSRIndex": "0x1A6", 5520 "MSRValue": "0x47FF", 5521 "CounterMask": "0", 5522 "Invert": "0", 5523 "AnyThread": "0", 5524 "EdgeDetect": "0", 5525 "PEBS": "0", 5526 "Offcore": "1" 5527 }, 5528 { 5529 "EventCode": "0xB7", 5530 "UMask": "0x1", 5531 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM", 5532 "BriefDescription": "Offcore requests satisfied by the local DRAM", 5533 "PublicDescription": "Offcore requests satisfied by the local DRAM", 5534 "Counter": "2", 5535 "SampleAfterValue": "100000", 5536 "MSRIndex": "0x1A6", 5537 "MSRValue": "0x40FF", 5538 "CounterMask": "0", 5539 "Invert": "0", 5540 "AnyThread": "0", 5541 "EdgeDetect": "0", 5542 "PEBS": "0", 5543 "Offcore": "1" 5544 }, 5545 { 5546 "EventCode": "0xB7", 5547 "UMask": "0x1", 5548 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE", 5549 "BriefDescription": "Offcore requests satisfied by a remote cache", 5550 "PublicDescription": "Offcore requests satisfied by a remote cache", 5551 "Counter": "2", 5552 "SampleAfterValue": "100000", 5553 "MSRIndex": "0x1A6", 5554 "MSRValue": "0x18FF", 5555 "CounterMask": "0", 5556 "Invert": "0", 5557 "AnyThread": "0", 5558 "EdgeDetect": "0", 5559 "PEBS": "0", 5560 "Offcore": "1" 5561 }, 5562 { 5563 "EventCode": "0xB7", 5564 "UMask": "0x1", 5565 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM", 5566 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 5567 "PublicDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 5568 "Counter": "2", 5569 "SampleAfterValue": "100000", 5570 "MSRIndex": "0x1A6", 5571 "MSRValue": "0x38FF", 5572 "CounterMask": "0", 5573 "Invert": "0", 5574 "AnyThread": "0", 5575 "EdgeDetect": "0", 5576 "PEBS": "0", 5577 "Offcore": "1" 5578 }, 5579 { 5580 "EventCode": "0xB7", 5581 "UMask": "0x1", 5582 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT", 5583 "BriefDescription": "Offcore requests that HIT in a remote cache", 5584 "PublicDescription": "Offcore requests that HIT in a remote cache", 5585 "Counter": "2", 5586 "SampleAfterValue": "100000", 5587 "MSRIndex": "0x1A6", 5588 "MSRValue": "0x10FF", 5589 "CounterMask": "0", 5590 "Invert": "0", 5591 "AnyThread": "0", 5592 "EdgeDetect": "0", 5593 "PEBS": "0", 5594 "Offcore": "1" 5595 }, 5596 { 5597 "EventCode": "0xB7", 5598 "UMask": "0x1", 5599 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM", 5600 "BriefDescription": "Offcore requests that HITM in a remote cache", 5601 "PublicDescription": "Offcore requests that HITM in a remote cache", 5602 "Counter": "2", 5603 "SampleAfterValue": "100000", 5604 "MSRIndex": "0x1A6", 5605 "MSRValue": "0x8FF", 5606 "CounterMask": "0", 5607 "Invert": "0", 5608 "AnyThread": "0", 5609 "EdgeDetect": "0", 5610 "PEBS": "0", 5611 "Offcore": "1" 5612 }, 5613 { 5614 "EventCode": "0xB7", 5615 "UMask": "0x1", 5616 "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM", 5617 "BriefDescription": "Offcore requests satisfied by a remote DRAM", 5618 "PublicDescription": "Offcore requests satisfied by a remote DRAM", 5619 "Counter": "2", 5620 "SampleAfterValue": "100000", 5621 "MSRIndex": "0x1A6", 5622 "MSRValue": "0x20FF", 5623 "CounterMask": "0", 5624 "Invert": "0", 5625 "AnyThread": "0", 5626 "EdgeDetect": "0", 5627 "PEBS": "0", 5628 "Offcore": "1" 5629 }, 5630 { 5631 "EventCode": "0xB7", 5632 "UMask": "0x1", 5633 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM", 5634 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 5635 "PublicDescription": "Offcore RFO requests satisfied by any cache or DRAM", 5636 "Counter": "2", 5637 "SampleAfterValue": "100000", 5638 "MSRIndex": "0x1A6", 5639 "MSRValue": "0x7F22", 5640 "CounterMask": "0", 5641 "Invert": "0", 5642 "AnyThread": "0", 5643 "EdgeDetect": "0", 5644 "PEBS": "0", 5645 "Offcore": "1" 5646 }, 5647 { 5648 "EventCode": "0xB7", 5649 "UMask": "0x1", 5650 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM", 5651 "BriefDescription": "Offcore RFO requests satisfied by any DRAM", 5652 "PublicDescription": "Offcore RFO requests satisfied by any DRAM", 5653 "Counter": "2", 5654 "SampleAfterValue": "100000", 5655 "MSRIndex": "0x1A6", 5656 "MSRValue": "0x6022", 5657 "CounterMask": "0", 5658 "Invert": "0", 5659 "AnyThread": "0", 5660 "EdgeDetect": "0", 5661 "PEBS": "0", 5662 "Offcore": "1" 5663 }, 5664 { 5665 "EventCode": "0xB7", 5666 "UMask": "0x1", 5667 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS", 5668 "BriefDescription": "Offcore RFO requests that missed the LLC", 5669 "PublicDescription": "Offcore RFO requests that missed the LLC", 5670 "Counter": "2", 5671 "SampleAfterValue": "100000", 5672 "MSRIndex": "0x1A6", 5673 "MSRValue": "0xF822", 5674 "CounterMask": "0", 5675 "Invert": "0", 5676 "AnyThread": "0", 5677 "EdgeDetect": "0", 5678 "PEBS": "0", 5679 "Offcore": "1" 5680 }, 5681 { 5682 "EventCode": "0xB7", 5683 "UMask": "0x1", 5684 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION", 5685 "BriefDescription": "All offcore RFO requests", 5686 "PublicDescription": "All offcore RFO requests", 5687 "Counter": "2", 5688 "SampleAfterValue": "100000", 5689 "MSRIndex": "0x1A6", 5690 "MSRValue": "0xFF22", 5691 "CounterMask": "0", 5692 "Invert": "0", 5693 "AnyThread": "0", 5694 "EdgeDetect": "0", 5695 "PEBS": "0", 5696 "Offcore": "1" 5697 }, 5698 { 5699 "EventCode": "0xB7", 5700 "UMask": "0x1", 5701 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO", 5702 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 5703 "PublicDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 5704 "Counter": "2", 5705 "SampleAfterValue": "100000", 5706 "MSRIndex": "0x1A6", 5707 "MSRValue": "0x8022", 5708 "CounterMask": "0", 5709 "Invert": "0", 5710 "AnyThread": "0", 5711 "EdgeDetect": "0", 5712 "PEBS": "0", 5713 "Offcore": "1" 5714 }, 5715 { 5716 "EventCode": "0xB7", 5717 "UMask": "0x1", 5718 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 5719 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 5720 "PublicDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 5721 "Counter": "2", 5722 "SampleAfterValue": "100000", 5723 "MSRIndex": "0x1A6", 5724 "MSRValue": "0x122", 5725 "CounterMask": "0", 5726 "Invert": "0", 5727 "AnyThread": "0", 5728 "EdgeDetect": "0", 5729 "PEBS": "0", 5730 "Offcore": "1" 5731 }, 5732 { 5733 "EventCode": "0xB7", 5734 "UMask": "0x1", 5735 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 5736 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 5737 "PublicDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 5738 "Counter": "2", 5739 "SampleAfterValue": "100000", 5740 "MSRIndex": "0x1A6", 5741 "MSRValue": "0x222", 5742 "CounterMask": "0", 5743 "Invert": "0", 5744 "AnyThread": "0", 5745 "EdgeDetect": "0", 5746 "PEBS": "0", 5747 "Offcore": "1" 5748 }, 5749 { 5750 "EventCode": "0xB7", 5751 "UMask": "0x1", 5752 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 5753 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 5754 "PublicDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 5755 "Counter": "2", 5756 "SampleAfterValue": "100000", 5757 "MSRIndex": "0x1A6", 5758 "MSRValue": "0x422", 5759 "CounterMask": "0", 5760 "Invert": "0", 5761 "AnyThread": "0", 5762 "EdgeDetect": "0", 5763 "PEBS": "0", 5764 "Offcore": "1" 5765 }, 5766 { 5767 "EventCode": "0xB7", 5768 "UMask": "0x1", 5769 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE", 5770 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 5771 "PublicDescription": "Offcore RFO requests satisfied by the LLC", 5772 "Counter": "2", 5773 "SampleAfterValue": "100000", 5774 "MSRIndex": "0x1A6", 5775 "MSRValue": "0x722", 5776 "CounterMask": "0", 5777 "Invert": "0", 5778 "AnyThread": "0", 5779 "EdgeDetect": "0", 5780 "PEBS": "0", 5781 "Offcore": "1" 5782 }, 5783 { 5784 "EventCode": "0xB7", 5785 "UMask": "0x1", 5786 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM", 5787 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 5788 "PublicDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 5789 "Counter": "2", 5790 "SampleAfterValue": "100000", 5791 "MSRIndex": "0x1A6", 5792 "MSRValue": "0x4722", 5793 "CounterMask": "0", 5794 "Invert": "0", 5795 "AnyThread": "0", 5796 "EdgeDetect": "0", 5797 "PEBS": "0", 5798 "Offcore": "1" 5799 }, 5800 { 5801 "EventCode": "0xB7", 5802 "UMask": "0x1", 5803 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM", 5804 "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", 5805 "PublicDescription": "Offcore RFO requests satisfied by the local DRAM", 5806 "Counter": "2", 5807 "SampleAfterValue": "100000", 5808 "MSRIndex": "0x1A6", 5809 "MSRValue": "0x4022", 5810 "CounterMask": "0", 5811 "Invert": "0", 5812 "AnyThread": "0", 5813 "EdgeDetect": "0", 5814 "PEBS": "0", 5815 "Offcore": "1" 5816 }, 5817 { 5818 "EventCode": "0xB7", 5819 "UMask": "0x1", 5820 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE", 5821 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 5822 "PublicDescription": "Offcore RFO requests satisfied by a remote cache", 5823 "Counter": "2", 5824 "SampleAfterValue": "100000", 5825 "MSRIndex": "0x1A6", 5826 "MSRValue": "0x1822", 5827 "CounterMask": "0", 5828 "Invert": "0", 5829 "AnyThread": "0", 5830 "EdgeDetect": "0", 5831 "PEBS": "0", 5832 "Offcore": "1" 5833 }, 5834 { 5835 "EventCode": "0xB7", 5836 "UMask": "0x1", 5837 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM", 5838 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 5839 "PublicDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 5840 "Counter": "2", 5841 "SampleAfterValue": "100000", 5842 "MSRIndex": "0x1A6", 5843 "MSRValue": "0x3822", 5844 "CounterMask": "0", 5845 "Invert": "0", 5846 "AnyThread": "0", 5847 "EdgeDetect": "0", 5848 "PEBS": "0", 5849 "Offcore": "1" 5850 }, 5851 { 5852 "EventCode": "0xB7", 5853 "UMask": "0x1", 5854 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT", 5855 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 5856 "PublicDescription": "Offcore RFO requests that HIT in a remote cache", 5857 "Counter": "2", 5858 "SampleAfterValue": "100000", 5859 "MSRIndex": "0x1A6", 5860 "MSRValue": "0x1022", 5861 "CounterMask": "0", 5862 "Invert": "0", 5863 "AnyThread": "0", 5864 "EdgeDetect": "0", 5865 "PEBS": "0", 5866 "Offcore": "1" 5867 }, 5868 { 5869 "EventCode": "0xB7", 5870 "UMask": "0x1", 5871 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM", 5872 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 5873 "PublicDescription": "Offcore RFO requests that HITM in a remote cache", 5874 "Counter": "2", 5875 "SampleAfterValue": "100000", 5876 "MSRIndex": "0x1A6", 5877 "MSRValue": "0x822", 5878 "CounterMask": "0", 5879 "Invert": "0", 5880 "AnyThread": "0", 5881 "EdgeDetect": "0", 5882 "PEBS": "0", 5883 "Offcore": "1" 5884 }, 5885 { 5886 "EventCode": "0xB7", 5887 "UMask": "0x1", 5888 "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM", 5889 "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", 5890 "PublicDescription": "Offcore RFO requests satisfied by a remote DRAM", 5891 "Counter": "2", 5892 "SampleAfterValue": "100000", 5893 "MSRIndex": "0x1A6", 5894 "MSRValue": "0x2022", 5895 "CounterMask": "0", 5896 "Invert": "0", 5897 "AnyThread": "0", 5898 "EdgeDetect": "0", 5899 "PEBS": "0", 5900 "Offcore": "1" 5901 }, 5902 { 5903 "EventCode": "0xB7", 5904 "UMask": "0x1", 5905 "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM", 5906 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 5907 "PublicDescription": "Offcore writebacks to any cache or DRAM.", 5908 "Counter": "2", 5909 "SampleAfterValue": "100000", 5910 "MSRIndex": "0x1A6", 5911 "MSRValue": "0x7F08", 5912 "CounterMask": "0", 5913 "Invert": "0", 5914 "AnyThread": "0", 5915 "EdgeDetect": "0", 5916 "PEBS": "0", 5917 "Offcore": "1" 5918 }, 5919 { 5920 "EventCode": "0xB7", 5921 "UMask": "0x1", 5922 "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_DRAM", 5923 "BriefDescription": "Offcore writebacks to any DRAM", 5924 "PublicDescription": "Offcore writebacks to any DRAM", 5925 "Counter": "2", 5926 "SampleAfterValue": "100000", 5927 "MSRIndex": "0x1A6", 5928 "MSRValue": "0x6008", 5929 "CounterMask": "0", 5930 "Invert": "0", 5931 "AnyThread": "0", 5932 "EdgeDetect": "0", 5933 "PEBS": "0", 5934 "Offcore": "1" 5935 }, 5936 { 5937 "EventCode": "0xB7", 5938 "UMask": "0x1", 5939 "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS", 5940 "BriefDescription": "Offcore writebacks that missed the LLC", 5941 "PublicDescription": "Offcore writebacks that missed the LLC", 5942 "Counter": "2", 5943 "SampleAfterValue": "100000", 5944 "MSRIndex": "0x1A6", 5945 "MSRValue": "0xF808", 5946 "CounterMask": "0", 5947 "Invert": "0", 5948 "AnyThread": "0", 5949 "EdgeDetect": "0", 5950 "PEBS": "0", 5951 "Offcore": "1" 5952 }, 5953 { 5954 "EventCode": "0xB7", 5955 "UMask": "0x1", 5956 "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION", 5957 "BriefDescription": "All offcore writebacks", 5958 "PublicDescription": "All offcore writebacks", 5959 "Counter": "2", 5960 "SampleAfterValue": "100000", 5961 "MSRIndex": "0x1A6", 5962 "MSRValue": "0xFF08", 5963 "CounterMask": "0", 5964 "Invert": "0", 5965 "AnyThread": "0", 5966 "EdgeDetect": "0", 5967 "PEBS": "0", 5968 "Offcore": "1" 5969 }, 5970 { 5971 "EventCode": "0xB7", 5972 "UMask": "0x1", 5973 "EventName": "OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO", 5974 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 5975 "PublicDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 5976 "Counter": "2", 5977 "SampleAfterValue": "100000", 5978 "MSRIndex": "0x1A6", 5979 "MSRValue": "0x8008", 5980 "CounterMask": "0", 5981 "Invert": "0", 5982 "AnyThread": "0", 5983 "EdgeDetect": "0", 5984 "PEBS": "0", 5985 "Offcore": "1" 5986 }, 5987 { 5988 "EventCode": "0xB7", 5989 "UMask": "0x1", 5990 "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE", 5991 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 5992 "PublicDescription": "Offcore writebacks to the LLC and not found in a sibling core", 5993 "Counter": "2", 5994 "SampleAfterValue": "100000", 5995 "MSRIndex": "0x1A6", 5996 "MSRValue": "0x108", 5997 "CounterMask": "0", 5998 "Invert": "0", 5999 "AnyThread": "0", 6000 "EdgeDetect": "0", 6001 "PEBS": "0", 6002 "Offcore": "1" 6003 }, 6004 { 6005 "EventCode": "0xB7", 6006 "UMask": "0x1", 6007 "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM", 6008 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 6009 "PublicDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 6010 "Counter": "2", 6011 "SampleAfterValue": "100000", 6012 "MSRIndex": "0x1A6", 6013 "MSRValue": "0x408", 6014 "CounterMask": "0", 6015 "Invert": "0", 6016 "AnyThread": "0", 6017 "EdgeDetect": "0", 6018 "PEBS": "0", 6019 "Offcore": "1" 6020 }, 6021 { 6022 "EventCode": "0xB7", 6023 "UMask": "0x1", 6024 "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE", 6025 "BriefDescription": "Offcore writebacks to the LLC", 6026 "PublicDescription": "Offcore writebacks to the LLC", 6027 "Counter": "2", 6028 "SampleAfterValue": "100000", 6029 "MSRIndex": "0x1A6", 6030 "MSRValue": "0x708", 6031 "CounterMask": "0", 6032 "Invert": "0", 6033 "AnyThread": "0", 6034 "EdgeDetect": "0", 6035 "PEBS": "0", 6036 "Offcore": "1" 6037 }, 6038 { 6039 "EventCode": "0xB7", 6040 "UMask": "0x1", 6041 "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM", 6042 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 6043 "PublicDescription": "Offcore writebacks to the LLC or local DRAM", 6044 "Counter": "2", 6045 "SampleAfterValue": "100000", 6046 "MSRIndex": "0x1A6", 6047 "MSRValue": "0x4708", 6048 "CounterMask": "0", 6049 "Invert": "0", 6050 "AnyThread": "0", 6051 "EdgeDetect": "0", 6052 "PEBS": "0", 6053 "Offcore": "1" 6054 }, 6055 { 6056 "EventCode": "0xB7", 6057 "UMask": "0x1", 6058 "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM", 6059 "BriefDescription": "Offcore writebacks to the local DRAM", 6060 "PublicDescription": "Offcore writebacks to the local DRAM", 6061 "Counter": "2", 6062 "SampleAfterValue": "100000", 6063 "MSRIndex": "0x1A6", 6064 "MSRValue": "0x4008", 6065 "CounterMask": "0", 6066 "Invert": "0", 6067 "AnyThread": "0", 6068 "EdgeDetect": "0", 6069 "PEBS": "0", 6070 "Offcore": "1" 6071 }, 6072 { 6073 "EventCode": "0xB7", 6074 "UMask": "0x1", 6075 "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE", 6076 "BriefDescription": "Offcore writebacks to a remote cache", 6077 "PublicDescription": "Offcore writebacks to a remote cache", 6078 "Counter": "2", 6079 "SampleAfterValue": "100000", 6080 "MSRIndex": "0x1A6", 6081 "MSRValue": "0x1808", 6082 "CounterMask": "0", 6083 "Invert": "0", 6084 "AnyThread": "0", 6085 "EdgeDetect": "0", 6086 "PEBS": "0", 6087 "Offcore": "1" 6088 }, 6089 { 6090 "EventCode": "0xB7", 6091 "UMask": "0x1", 6092 "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM", 6093 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 6094 "PublicDescription": "Offcore writebacks to a remote cache or remote DRAM", 6095 "Counter": "2", 6096 "SampleAfterValue": "100000", 6097 "MSRIndex": "0x1A6", 6098 "MSRValue": "0x3808", 6099 "CounterMask": "0", 6100 "Invert": "0", 6101 "AnyThread": "0", 6102 "EdgeDetect": "0", 6103 "PEBS": "0", 6104 "Offcore": "1" 6105 }, 6106 { 6107 "EventCode": "0xB7", 6108 "UMask": "0x1", 6109 "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT", 6110 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 6111 "PublicDescription": "Offcore writebacks that HIT in a remote cache", 6112 "Counter": "2", 6113 "SampleAfterValue": "100000", 6114 "MSRIndex": "0x1A6", 6115 "MSRValue": "0x1008", 6116 "CounterMask": "0", 6117 "Invert": "0", 6118 "AnyThread": "0", 6119 "EdgeDetect": "0", 6120 "PEBS": "0", 6121 "Offcore": "1" 6122 }, 6123 { 6124 "EventCode": "0xB7", 6125 "UMask": "0x1", 6126 "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM", 6127 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 6128 "PublicDescription": "Offcore writebacks that HITM in a remote cache", 6129 "Counter": "2", 6130 "SampleAfterValue": "100000", 6131 "MSRIndex": "0x1A6", 6132 "MSRValue": "0x808", 6133 "CounterMask": "0", 6134 "Invert": "0", 6135 "AnyThread": "0", 6136 "EdgeDetect": "0", 6137 "PEBS": "0", 6138 "Offcore": "1" 6139 }, 6140 { 6141 "EventCode": "0xB7", 6142 "UMask": "0x1", 6143 "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM", 6144 "BriefDescription": "Offcore writebacks to a remote DRAM", 6145 "PublicDescription": "Offcore writebacks to a remote DRAM", 6146 "Counter": "2", 6147 "SampleAfterValue": "100000", 6148 "MSRIndex": "0x1A6", 6149 "MSRValue": "0x2008", 6150 "CounterMask": "0", 6151 "Invert": "0", 6152 "AnyThread": "0", 6153 "EdgeDetect": "0", 6154 "PEBS": "0", 6155 "Offcore": "1" 6156 }, 6157 { 6158 "EventCode": "0xB7", 6159 "UMask": "0x1", 6160 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM", 6161 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 6162 "PublicDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 6163 "Counter": "2", 6164 "SampleAfterValue": "100000", 6165 "MSRIndex": "0x1A6", 6166 "MSRValue": "0x7F77", 6167 "CounterMask": "0", 6168 "Invert": "0", 6169 "AnyThread": "0", 6170 "EdgeDetect": "0", 6171 "PEBS": "0", 6172 "Offcore": "1" 6173 }, 6174 { 6175 "EventCode": "0xB7", 6176 "UMask": "0x1", 6177 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM", 6178 "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", 6179 "PublicDescription": "Offcore code or data read requests satisfied by any DRAM", 6180 "Counter": "2", 6181 "SampleAfterValue": "100000", 6182 "MSRIndex": "0x1A6", 6183 "MSRValue": "0x6077", 6184 "CounterMask": "0", 6185 "Invert": "0", 6186 "AnyThread": "0", 6187 "EdgeDetect": "0", 6188 "PEBS": "0", 6189 "Offcore": "1" 6190 }, 6191 { 6192 "EventCode": "0xB7", 6193 "UMask": "0x1", 6194 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS", 6195 "BriefDescription": "Offcore code or data read requests that missed the LLC", 6196 "PublicDescription": "Offcore code or data read requests that missed the LLC", 6197 "Counter": "2", 6198 "SampleAfterValue": "100000", 6199 "MSRIndex": "0x1A6", 6200 "MSRValue": "0xF877", 6201 "CounterMask": "0", 6202 "Invert": "0", 6203 "AnyThread": "0", 6204 "EdgeDetect": "0", 6205 "PEBS": "0", 6206 "Offcore": "1" 6207 }, 6208 { 6209 "EventCode": "0xB7", 6210 "UMask": "0x1", 6211 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION", 6212 "BriefDescription": "All offcore code or data read requests", 6213 "PublicDescription": "All offcore code or data read requests", 6214 "Counter": "2", 6215 "SampleAfterValue": "100000", 6216 "MSRIndex": "0x1A6", 6217 "MSRValue": "0xFF77", 6218 "CounterMask": "0", 6219 "Invert": "0", 6220 "AnyThread": "0", 6221 "EdgeDetect": "0", 6222 "PEBS": "0", 6223 "Offcore": "1" 6224 }, 6225 { 6226 "EventCode": "0xB7", 6227 "UMask": "0x1", 6228 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO", 6229 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 6230 "PublicDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 6231 "Counter": "2", 6232 "SampleAfterValue": "100000", 6233 "MSRIndex": "0x1A6", 6234 "MSRValue": "0x8077", 6235 "CounterMask": "0", 6236 "Invert": "0", 6237 "AnyThread": "0", 6238 "EdgeDetect": "0", 6239 "PEBS": "0", 6240 "Offcore": "1" 6241 }, 6242 { 6243 "EventCode": "0xB7", 6244 "UMask": "0x1", 6245 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 6246 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 6247 "PublicDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 6248 "Counter": "2", 6249 "SampleAfterValue": "100000", 6250 "MSRIndex": "0x1A6", 6251 "MSRValue": "0x177", 6252 "CounterMask": "0", 6253 "Invert": "0", 6254 "AnyThread": "0", 6255 "EdgeDetect": "0", 6256 "PEBS": "0", 6257 "Offcore": "1" 6258 }, 6259 { 6260 "EventCode": "0xB7", 6261 "UMask": "0x1", 6262 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 6263 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 6264 "PublicDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 6265 "Counter": "2", 6266 "SampleAfterValue": "100000", 6267 "MSRIndex": "0x1A6", 6268 "MSRValue": "0x277", 6269 "CounterMask": "0", 6270 "Invert": "0", 6271 "AnyThread": "0", 6272 "EdgeDetect": "0", 6273 "PEBS": "0", 6274 "Offcore": "1" 6275 }, 6276 { 6277 "EventCode": "0xB7", 6278 "UMask": "0x1", 6279 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 6280 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 6281 "PublicDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 6282 "Counter": "2", 6283 "SampleAfterValue": "100000", 6284 "MSRIndex": "0x1A6", 6285 "MSRValue": "0x477", 6286 "CounterMask": "0", 6287 "Invert": "0", 6288 "AnyThread": "0", 6289 "EdgeDetect": "0", 6290 "PEBS": "0", 6291 "Offcore": "1" 6292 }, 6293 { 6294 "EventCode": "0xB7", 6295 "UMask": "0x1", 6296 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE", 6297 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 6298 "PublicDescription": "Offcore code or data read requests satisfied by the LLC", 6299 "Counter": "2", 6300 "SampleAfterValue": "100000", 6301 "MSRIndex": "0x1A6", 6302 "MSRValue": "0x777", 6303 "CounterMask": "0", 6304 "Invert": "0", 6305 "AnyThread": "0", 6306 "EdgeDetect": "0", 6307 "PEBS": "0", 6308 "Offcore": "1" 6309 }, 6310 { 6311 "EventCode": "0xB7", 6312 "UMask": "0x1", 6313 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM", 6314 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 6315 "PublicDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 6316 "Counter": "2", 6317 "SampleAfterValue": "100000", 6318 "MSRIndex": "0x1A6", 6319 "MSRValue": "0x4777", 6320 "CounterMask": "0", 6321 "Invert": "0", 6322 "AnyThread": "0", 6323 "EdgeDetect": "0", 6324 "PEBS": "0", 6325 "Offcore": "1" 6326 }, 6327 { 6328 "EventCode": "0xB7", 6329 "UMask": "0x1", 6330 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM", 6331 "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", 6332 "PublicDescription": "Offcore code or data read requests satisfied by the local DRAM", 6333 "Counter": "2", 6334 "SampleAfterValue": "100000", 6335 "MSRIndex": "0x1A6", 6336 "MSRValue": "0x4077", 6337 "CounterMask": "0", 6338 "Invert": "0", 6339 "AnyThread": "0", 6340 "EdgeDetect": "0", 6341 "PEBS": "0", 6342 "Offcore": "1" 6343 }, 6344 { 6345 "EventCode": "0xB7", 6346 "UMask": "0x1", 6347 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE", 6348 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 6349 "PublicDescription": "Offcore code or data read requests satisfied by a remote cache", 6350 "Counter": "2", 6351 "SampleAfterValue": "100000", 6352 "MSRIndex": "0x1A6", 6353 "MSRValue": "0x1877", 6354 "CounterMask": "0", 6355 "Invert": "0", 6356 "AnyThread": "0", 6357 "EdgeDetect": "0", 6358 "PEBS": "0", 6359 "Offcore": "1" 6360 }, 6361 { 6362 "EventCode": "0xB7", 6363 "UMask": "0x1", 6364 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM", 6365 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 6366 "PublicDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 6367 "Counter": "2", 6368 "SampleAfterValue": "100000", 6369 "MSRIndex": "0x1A6", 6370 "MSRValue": "0x3877", 6371 "CounterMask": "0", 6372 "Invert": "0", 6373 "AnyThread": "0", 6374 "EdgeDetect": "0", 6375 "PEBS": "0", 6376 "Offcore": "1" 6377 }, 6378 { 6379 "EventCode": "0xB7", 6380 "UMask": "0x1", 6381 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT", 6382 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 6383 "PublicDescription": "Offcore code or data read requests that HIT in a remote cache", 6384 "Counter": "2", 6385 "SampleAfterValue": "100000", 6386 "MSRIndex": "0x1A6", 6387 "MSRValue": "0x1077", 6388 "CounterMask": "0", 6389 "Invert": "0", 6390 "AnyThread": "0", 6391 "EdgeDetect": "0", 6392 "PEBS": "0", 6393 "Offcore": "1" 6394 }, 6395 { 6396 "EventCode": "0xB7", 6397 "UMask": "0x1", 6398 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM", 6399 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 6400 "PublicDescription": "Offcore code or data read requests that HITM in a remote cache", 6401 "Counter": "2", 6402 "SampleAfterValue": "100000", 6403 "MSRIndex": "0x1A6", 6404 "MSRValue": "0x877", 6405 "CounterMask": "0", 6406 "Invert": "0", 6407 "AnyThread": "0", 6408 "EdgeDetect": "0", 6409 "PEBS": "0", 6410 "Offcore": "1" 6411 }, 6412 { 6413 "EventCode": "0xB7", 6414 "UMask": "0x1", 6415 "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM", 6416 "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", 6417 "PublicDescription": "Offcore code or data read requests satisfied by a remote DRAM", 6418 "Counter": "2", 6419 "SampleAfterValue": "100000", 6420 "MSRIndex": "0x1A6", 6421 "MSRValue": "0x2077", 6422 "CounterMask": "0", 6423 "Invert": "0", 6424 "AnyThread": "0", 6425 "EdgeDetect": "0", 6426 "PEBS": "0", 6427 "Offcore": "1" 6428 }, 6429 { 6430 "EventCode": "0xB7", 6431 "UMask": "0x1", 6432 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM", 6433 "BriefDescription": "Offcore request = all data, response = any cache_dram", 6434 "PublicDescription": "Offcore request = all data, response = any cache_dram", 6435 "Counter": "2", 6436 "SampleAfterValue": "100000", 6437 "MSRIndex": "0x1A6", 6438 "MSRValue": "0x7F33", 6439 "CounterMask": "0", 6440 "Invert": "0", 6441 "AnyThread": "0", 6442 "EdgeDetect": "0", 6443 "PEBS": "0", 6444 "Offcore": "1" 6445 }, 6446 { 6447 "EventCode": "0xB7", 6448 "UMask": "0x1", 6449 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM", 6450 "BriefDescription": "Offcore request = all data, response = any DRAM", 6451 "PublicDescription": "Offcore request = all data, response = any DRAM", 6452 "Counter": "2", 6453 "SampleAfterValue": "100000", 6454 "MSRIndex": "0x1A6", 6455 "MSRValue": "0x6033", 6456 "CounterMask": "0", 6457 "Invert": "0", 6458 "AnyThread": "0", 6459 "EdgeDetect": "0", 6460 "PEBS": "0", 6461 "Offcore": "1" 6462 }, 6463 { 6464 "EventCode": "0xB7", 6465 "UMask": "0x1", 6466 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS", 6467 "BriefDescription": "Offcore request = all data, response = any LLC miss", 6468 "PublicDescription": "Offcore request = all data, response = any LLC miss", 6469 "Counter": "2", 6470 "SampleAfterValue": "100000", 6471 "MSRIndex": "0x1A6", 6472 "MSRValue": "0xF833", 6473 "CounterMask": "0", 6474 "Invert": "0", 6475 "AnyThread": "0", 6476 "EdgeDetect": "0", 6477 "PEBS": "0", 6478 "Offcore": "1" 6479 }, 6480 { 6481 "EventCode": "0xB7", 6482 "UMask": "0x1", 6483 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION", 6484 "BriefDescription": "Offcore request = all data, response = any location", 6485 "PublicDescription": "Offcore request = all data, response = any location", 6486 "Counter": "2", 6487 "SampleAfterValue": "100000", 6488 "MSRIndex": "0x1A6", 6489 "MSRValue": "0xFF33", 6490 "CounterMask": "0", 6491 "Invert": "0", 6492 "AnyThread": "0", 6493 "EdgeDetect": "0", 6494 "PEBS": "0", 6495 "Offcore": "1" 6496 }, 6497 { 6498 "EventCode": "0xB7", 6499 "UMask": "0x1", 6500 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO", 6501 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", 6502 "PublicDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", 6503 "Counter": "2", 6504 "SampleAfterValue": "100000", 6505 "MSRIndex": "0x1A6", 6506 "MSRValue": "0x8033", 6507 "CounterMask": "0", 6508 "Invert": "0", 6509 "AnyThread": "0", 6510 "EdgeDetect": "0", 6511 "PEBS": "0", 6512 "Offcore": "1" 6513 }, 6514 { 6515 "EventCode": "0xB7", 6516 "UMask": "0x1", 6517 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE", 6518 "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", 6519 "PublicDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", 6520 "Counter": "2", 6521 "SampleAfterValue": "100000", 6522 "MSRIndex": "0x1A6", 6523 "MSRValue": "0x133", 6524 "CounterMask": "0", 6525 "Invert": "0", 6526 "AnyThread": "0", 6527 "EdgeDetect": "0", 6528 "PEBS": "0", 6529 "Offcore": "1" 6530 }, 6531 { 6532 "EventCode": "0xB7", 6533 "UMask": "0x1", 6534 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 6535 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", 6536 "PublicDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", 6537 "Counter": "2", 6538 "SampleAfterValue": "100000", 6539 "MSRIndex": "0x1A6", 6540 "MSRValue": "0x233", 6541 "CounterMask": "0", 6542 "Invert": "0", 6543 "AnyThread": "0", 6544 "EdgeDetect": "0", 6545 "PEBS": "0", 6546 "Offcore": "1" 6547 }, 6548 { 6549 "EventCode": "0xB7", 6550 "UMask": "0x1", 6551 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 6552 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", 6553 "PublicDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", 6554 "Counter": "2", 6555 "SampleAfterValue": "100000", 6556 "MSRIndex": "0x1A6", 6557 "MSRValue": "0x433", 6558 "CounterMask": "0", 6559 "Invert": "0", 6560 "AnyThread": "0", 6561 "EdgeDetect": "0", 6562 "PEBS": "0", 6563 "Offcore": "1" 6564 }, 6565 { 6566 "EventCode": "0xB7", 6567 "UMask": "0x1", 6568 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE", 6569 "BriefDescription": "Offcore request = all data, response = local cache", 6570 "PublicDescription": "Offcore request = all data, response = local cache", 6571 "Counter": "2", 6572 "SampleAfterValue": "100000", 6573 "MSRIndex": "0x1A6", 6574 "MSRValue": "0x733", 6575 "CounterMask": "0", 6576 "Invert": "0", 6577 "AnyThread": "0", 6578 "EdgeDetect": "0", 6579 "PEBS": "0", 6580 "Offcore": "1" 6581 }, 6582 { 6583 "EventCode": "0xB7", 6584 "UMask": "0x1", 6585 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM", 6586 "BriefDescription": "Offcore request = all data, response = local cache or dram", 6587 "PublicDescription": "Offcore request = all data, response = local cache or dram", 6588 "Counter": "2", 6589 "SampleAfterValue": "100000", 6590 "MSRIndex": "0x1A6", 6591 "MSRValue": "0x4733", 6592 "CounterMask": "0", 6593 "Invert": "0", 6594 "AnyThread": "0", 6595 "EdgeDetect": "0", 6596 "PEBS": "0", 6597 "Offcore": "1" 6598 }, 6599 { 6600 "EventCode": "0xB7", 6601 "UMask": "0x1", 6602 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM", 6603 "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", 6604 "PublicDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", 6605 "Counter": "2", 6606 "SampleAfterValue": "100000", 6607 "MSRIndex": "0x1A6", 6608 "MSRValue": "0x4033", 6609 "CounterMask": "0", 6610 "Invert": "0", 6611 "AnyThread": "0", 6612 "EdgeDetect": "0", 6613 "PEBS": "0", 6614 "Offcore": "1" 6615 }, 6616 { 6617 "EventCode": "0xB7", 6618 "UMask": "0x1", 6619 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE", 6620 "BriefDescription": "Offcore request = all data, response = remote cache", 6621 "PublicDescription": "Offcore request = all data, response = remote cache", 6622 "Counter": "2", 6623 "SampleAfterValue": "100000", 6624 "MSRIndex": "0x1A6", 6625 "MSRValue": "0x1833", 6626 "CounterMask": "0", 6627 "Invert": "0", 6628 "AnyThread": "0", 6629 "EdgeDetect": "0", 6630 "PEBS": "0", 6631 "Offcore": "1" 6632 }, 6633 { 6634 "EventCode": "0xB7", 6635 "UMask": "0x1", 6636 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM", 6637 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 6638 "PublicDescription": "Offcore request = all data, response = remote cache or dram", 6639 "Counter": "2", 6640 "SampleAfterValue": "100000", 6641 "MSRIndex": "0x1A6", 6642 "MSRValue": "0x3833", 6643 "CounterMask": "0", 6644 "Invert": "0", 6645 "AnyThread": "0", 6646 "EdgeDetect": "0", 6647 "PEBS": "0", 6648 "Offcore": "1" 6649 }, 6650 { 6651 "EventCode": "0xB7", 6652 "UMask": "0x1", 6653 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT", 6654 "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", 6655 "PublicDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", 6656 "Counter": "2", 6657 "SampleAfterValue": "100000", 6658 "MSRIndex": "0x1A6", 6659 "MSRValue": "0x1033", 6660 "CounterMask": "0", 6661 "Invert": "0", 6662 "AnyThread": "0", 6663 "EdgeDetect": "0", 6664 "PEBS": "0", 6665 "Offcore": "1" 6666 }, 6667 { 6668 "EventCode": "0xB7", 6669 "UMask": "0x1", 6670 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM", 6671 "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", 6672 "PublicDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", 6673 "Counter": "2", 6674 "SampleAfterValue": "100000", 6675 "MSRIndex": "0x1A6", 6676 "MSRValue": "0x833", 6677 "CounterMask": "0", 6678 "Invert": "0", 6679 "AnyThread": "0", 6680 "EdgeDetect": "0", 6681 "PEBS": "0", 6682 "Offcore": "1" 6683 }, 6684 { 6685 "EventCode": "0xB7", 6686 "UMask": "0x1", 6687 "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM", 6688 "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", 6689 "PublicDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", 6690 "Counter": "2", 6691 "SampleAfterValue": "100000", 6692 "MSRIndex": "0x1A6", 6693 "MSRValue": "0x2033", 6694 "CounterMask": "0", 6695 "Invert": "0", 6696 "AnyThread": "0", 6697 "EdgeDetect": "0", 6698 "PEBS": "0", 6699 "Offcore": "1" 6700 }, 6701 { 6702 "EventCode": "0xB7", 6703 "UMask": "0x1", 6704 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM", 6705 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 6706 "PublicDescription": "Offcore demand data requests satisfied by any cache or DRAM", 6707 "Counter": "2", 6708 "SampleAfterValue": "100000", 6709 "MSRIndex": "0x1A6", 6710 "MSRValue": "0x7F03", 6711 "CounterMask": "0", 6712 "Invert": "0", 6713 "AnyThread": "0", 6714 "EdgeDetect": "0", 6715 "PEBS": "0", 6716 "Offcore": "1" 6717 }, 6718 { 6719 "EventCode": "0xB7", 6720 "UMask": "0x1", 6721 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM", 6722 "BriefDescription": "Offcore demand data requests satisfied by any DRAM", 6723 "PublicDescription": "Offcore demand data requests satisfied by any DRAM", 6724 "Counter": "2", 6725 "SampleAfterValue": "100000", 6726 "MSRIndex": "0x1A6", 6727 "MSRValue": "0x6003", 6728 "CounterMask": "0", 6729 "Invert": "0", 6730 "AnyThread": "0", 6731 "EdgeDetect": "0", 6732 "PEBS": "0", 6733 "Offcore": "1" 6734 }, 6735 { 6736 "EventCode": "0xB7", 6737 "UMask": "0x1", 6738 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS", 6739 "BriefDescription": "Offcore demand data requests that missed the LLC", 6740 "PublicDescription": "Offcore demand data requests that missed the LLC", 6741 "Counter": "2", 6742 "SampleAfterValue": "100000", 6743 "MSRIndex": "0x1A6", 6744 "MSRValue": "0xF803", 6745 "CounterMask": "0", 6746 "Invert": "0", 6747 "AnyThread": "0", 6748 "EdgeDetect": "0", 6749 "PEBS": "0", 6750 "Offcore": "1" 6751 }, 6752 { 6753 "EventCode": "0xB7", 6754 "UMask": "0x1", 6755 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION", 6756 "BriefDescription": "All offcore demand data requests", 6757 "PublicDescription": "All offcore demand data requests", 6758 "Counter": "2", 6759 "SampleAfterValue": "100000", 6760 "MSRIndex": "0x1A6", 6761 "MSRValue": "0xFF03", 6762 "CounterMask": "0", 6763 "Invert": "0", 6764 "AnyThread": "0", 6765 "EdgeDetect": "0", 6766 "PEBS": "0", 6767 "Offcore": "1" 6768 }, 6769 { 6770 "EventCode": "0xB7", 6771 "UMask": "0x1", 6772 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO", 6773 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 6774 "PublicDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 6775 "Counter": "2", 6776 "SampleAfterValue": "100000", 6777 "MSRIndex": "0x1A6", 6778 "MSRValue": "0x8003", 6779 "CounterMask": "0", 6780 "Invert": "0", 6781 "AnyThread": "0", 6782 "EdgeDetect": "0", 6783 "PEBS": "0", 6784 "Offcore": "1" 6785 }, 6786 { 6787 "EventCode": "0xB7", 6788 "UMask": "0x1", 6789 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 6790 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 6791 "PublicDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 6792 "Counter": "2", 6793 "SampleAfterValue": "100000", 6794 "MSRIndex": "0x1A6", 6795 "MSRValue": "0x103", 6796 "CounterMask": "0", 6797 "Invert": "0", 6798 "AnyThread": "0", 6799 "EdgeDetect": "0", 6800 "PEBS": "0", 6801 "Offcore": "1" 6802 }, 6803 { 6804 "EventCode": "0xB7", 6805 "UMask": "0x1", 6806 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 6807 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 6808 "PublicDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 6809 "Counter": "2", 6810 "SampleAfterValue": "100000", 6811 "MSRIndex": "0x1A6", 6812 "MSRValue": "0x203", 6813 "CounterMask": "0", 6814 "Invert": "0", 6815 "AnyThread": "0", 6816 "EdgeDetect": "0", 6817 "PEBS": "0", 6818 "Offcore": "1" 6819 }, 6820 { 6821 "EventCode": "0xB7", 6822 "UMask": "0x1", 6823 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 6824 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 6825 "PublicDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 6826 "Counter": "2", 6827 "SampleAfterValue": "100000", 6828 "MSRIndex": "0x1A6", 6829 "MSRValue": "0x403", 6830 "CounterMask": "0", 6831 "Invert": "0", 6832 "AnyThread": "0", 6833 "EdgeDetect": "0", 6834 "PEBS": "0", 6835 "Offcore": "1" 6836 }, 6837 { 6838 "EventCode": "0xB7", 6839 "UMask": "0x1", 6840 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE", 6841 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 6842 "PublicDescription": "Offcore demand data requests satisfied by the LLC", 6843 "Counter": "2", 6844 "SampleAfterValue": "100000", 6845 "MSRIndex": "0x1A6", 6846 "MSRValue": "0x703", 6847 "CounterMask": "0", 6848 "Invert": "0", 6849 "AnyThread": "0", 6850 "EdgeDetect": "0", 6851 "PEBS": "0", 6852 "Offcore": "1" 6853 }, 6854 { 6855 "EventCode": "0xB7", 6856 "UMask": "0x1", 6857 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM", 6858 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 6859 "PublicDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 6860 "Counter": "2", 6861 "SampleAfterValue": "100000", 6862 "MSRIndex": "0x1A6", 6863 "MSRValue": "0x4703", 6864 "CounterMask": "0", 6865 "Invert": "0", 6866 "AnyThread": "0", 6867 "EdgeDetect": "0", 6868 "PEBS": "0", 6869 "Offcore": "1" 6870 }, 6871 { 6872 "EventCode": "0xB7", 6873 "UMask": "0x1", 6874 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM", 6875 "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", 6876 "PublicDescription": "Offcore demand data requests satisfied by the local DRAM", 6877 "Counter": "2", 6878 "SampleAfterValue": "100000", 6879 "MSRIndex": "0x1A6", 6880 "MSRValue": "0x4003", 6881 "CounterMask": "0", 6882 "Invert": "0", 6883 "AnyThread": "0", 6884 "EdgeDetect": "0", 6885 "PEBS": "0", 6886 "Offcore": "1" 6887 }, 6888 { 6889 "EventCode": "0xB7", 6890 "UMask": "0x1", 6891 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE", 6892 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 6893 "PublicDescription": "Offcore demand data requests satisfied by a remote cache", 6894 "Counter": "2", 6895 "SampleAfterValue": "100000", 6896 "MSRIndex": "0x1A6", 6897 "MSRValue": "0x1803", 6898 "CounterMask": "0", 6899 "Invert": "0", 6900 "AnyThread": "0", 6901 "EdgeDetect": "0", 6902 "PEBS": "0", 6903 "Offcore": "1" 6904 }, 6905 { 6906 "EventCode": "0xB7", 6907 "UMask": "0x1", 6908 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM", 6909 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 6910 "PublicDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 6911 "Counter": "2", 6912 "SampleAfterValue": "100000", 6913 "MSRIndex": "0x1A6", 6914 "MSRValue": "0x3803", 6915 "CounterMask": "0", 6916 "Invert": "0", 6917 "AnyThread": "0", 6918 "EdgeDetect": "0", 6919 "PEBS": "0", 6920 "Offcore": "1" 6921 }, 6922 { 6923 "EventCode": "0xB7", 6924 "UMask": "0x1", 6925 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT", 6926 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 6927 "PublicDescription": "Offcore demand data requests that HIT in a remote cache", 6928 "Counter": "2", 6929 "SampleAfterValue": "100000", 6930 "MSRIndex": "0x1A6", 6931 "MSRValue": "0x1003", 6932 "CounterMask": "0", 6933 "Invert": "0", 6934 "AnyThread": "0", 6935 "EdgeDetect": "0", 6936 "PEBS": "0", 6937 "Offcore": "1" 6938 }, 6939 { 6940 "EventCode": "0xB7", 6941 "UMask": "0x1", 6942 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM", 6943 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 6944 "PublicDescription": "Offcore demand data requests that HITM in a remote cache", 6945 "Counter": "2", 6946 "SampleAfterValue": "100000", 6947 "MSRIndex": "0x1A6", 6948 "MSRValue": "0x803", 6949 "CounterMask": "0", 6950 "Invert": "0", 6951 "AnyThread": "0", 6952 "EdgeDetect": "0", 6953 "PEBS": "0", 6954 "Offcore": "1" 6955 }, 6956 { 6957 "EventCode": "0xB7", 6958 "UMask": "0x1", 6959 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM", 6960 "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", 6961 "PublicDescription": "Offcore demand data requests satisfied by a remote DRAM", 6962 "Counter": "2", 6963 "SampleAfterValue": "100000", 6964 "MSRIndex": "0x1A6", 6965 "MSRValue": "0x2003", 6966 "CounterMask": "0", 6967 "Invert": "0", 6968 "AnyThread": "0", 6969 "EdgeDetect": "0", 6970 "PEBS": "0", 6971 "Offcore": "1" 6972 }, 6973 { 6974 "EventCode": "0xB7", 6975 "UMask": "0x1", 6976 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM", 6977 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 6978 "PublicDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 6979 "Counter": "2", 6980 "SampleAfterValue": "100000", 6981 "MSRIndex": "0x1A6", 6982 "MSRValue": "0x7F01", 6983 "CounterMask": "0", 6984 "Invert": "0", 6985 "AnyThread": "0", 6986 "EdgeDetect": "0", 6987 "PEBS": "0", 6988 "Offcore": "1" 6989 }, 6990 { 6991 "EventCode": "0xB7", 6992 "UMask": "0x1", 6993 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM", 6994 "BriefDescription": "Offcore demand data reads satisfied by any DRAM", 6995 "PublicDescription": "Offcore demand data reads satisfied by any DRAM", 6996 "Counter": "2", 6997 "SampleAfterValue": "100000", 6998 "MSRIndex": "0x1A6", 6999 "MSRValue": "0x6001", 7000 "CounterMask": "0", 7001 "Invert": "0", 7002 "AnyThread": "0", 7003 "EdgeDetect": "0", 7004 "PEBS": "0", 7005 "Offcore": "1" 7006 }, 7007 { 7008 "EventCode": "0xB7", 7009 "UMask": "0x1", 7010 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS", 7011 "BriefDescription": "Offcore demand data reads that missed the LLC", 7012 "PublicDescription": "Offcore demand data reads that missed the LLC", 7013 "Counter": "2", 7014 "SampleAfterValue": "100000", 7015 "MSRIndex": "0x1A6", 7016 "MSRValue": "0xF801", 7017 "CounterMask": "0", 7018 "Invert": "0", 7019 "AnyThread": "0", 7020 "EdgeDetect": "0", 7021 "PEBS": "0", 7022 "Offcore": "1" 7023 }, 7024 { 7025 "EventCode": "0xB7", 7026 "UMask": "0x1", 7027 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION", 7028 "BriefDescription": "All offcore demand data reads", 7029 "PublicDescription": "All offcore demand data reads", 7030 "Counter": "2", 7031 "SampleAfterValue": "100000", 7032 "MSRIndex": "0x1A6", 7033 "MSRValue": "0xFF01", 7034 "CounterMask": "0", 7035 "Invert": "0", 7036 "AnyThread": "0", 7037 "EdgeDetect": "0", 7038 "PEBS": "0", 7039 "Offcore": "1" 7040 }, 7041 { 7042 "EventCode": "0xB7", 7043 "UMask": "0x1", 7044 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO", 7045 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 7046 "PublicDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 7047 "Counter": "2", 7048 "SampleAfterValue": "100000", 7049 "MSRIndex": "0x1A6", 7050 "MSRValue": "0x8001", 7051 "CounterMask": "0", 7052 "Invert": "0", 7053 "AnyThread": "0", 7054 "EdgeDetect": "0", 7055 "PEBS": "0", 7056 "Offcore": "1" 7057 }, 7058 { 7059 "EventCode": "0xB7", 7060 "UMask": "0x1", 7061 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 7062 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 7063 "PublicDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 7064 "Counter": "2", 7065 "SampleAfterValue": "100000", 7066 "MSRIndex": "0x1A6", 7067 "MSRValue": "0x101", 7068 "CounterMask": "0", 7069 "Invert": "0", 7070 "AnyThread": "0", 7071 "EdgeDetect": "0", 7072 "PEBS": "0", 7073 "Offcore": "1" 7074 }, 7075 { 7076 "EventCode": "0xB7", 7077 "UMask": "0x1", 7078 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 7079 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 7080 "PublicDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 7081 "Counter": "2", 7082 "SampleAfterValue": "100000", 7083 "MSRIndex": "0x1A6", 7084 "MSRValue": "0x201", 7085 "CounterMask": "0", 7086 "Invert": "0", 7087 "AnyThread": "0", 7088 "EdgeDetect": "0", 7089 "PEBS": "0", 7090 "Offcore": "1" 7091 }, 7092 { 7093 "EventCode": "0xB7", 7094 "UMask": "0x1", 7095 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 7096 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 7097 "PublicDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 7098 "Counter": "2", 7099 "SampleAfterValue": "100000", 7100 "MSRIndex": "0x1A6", 7101 "MSRValue": "0x401", 7102 "CounterMask": "0", 7103 "Invert": "0", 7104 "AnyThread": "0", 7105 "EdgeDetect": "0", 7106 "PEBS": "0", 7107 "Offcore": "1" 7108 }, 7109 { 7110 "EventCode": "0xB7", 7111 "UMask": "0x1", 7112 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE", 7113 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 7114 "PublicDescription": "Offcore demand data reads satisfied by the LLC", 7115 "Counter": "2", 7116 "SampleAfterValue": "100000", 7117 "MSRIndex": "0x1A6", 7118 "MSRValue": "0x701", 7119 "CounterMask": "0", 7120 "Invert": "0", 7121 "AnyThread": "0", 7122 "EdgeDetect": "0", 7123 "PEBS": "0", 7124 "Offcore": "1" 7125 }, 7126 { 7127 "EventCode": "0xB7", 7128 "UMask": "0x1", 7129 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 7130 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 7131 "PublicDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 7132 "Counter": "2", 7133 "SampleAfterValue": "100000", 7134 "MSRIndex": "0x1A6", 7135 "MSRValue": "0x4701", 7136 "CounterMask": "0", 7137 "Invert": "0", 7138 "AnyThread": "0", 7139 "EdgeDetect": "0", 7140 "PEBS": "0", 7141 "Offcore": "1" 7142 }, 7143 { 7144 "EventCode": "0xB7", 7145 "UMask": "0x1", 7146 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM", 7147 "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", 7148 "PublicDescription": "Offcore demand data reads satisfied by the local DRAM", 7149 "Counter": "2", 7150 "SampleAfterValue": "100000", 7151 "MSRIndex": "0x1A6", 7152 "MSRValue": "0x4001", 7153 "CounterMask": "0", 7154 "Invert": "0", 7155 "AnyThread": "0", 7156 "EdgeDetect": "0", 7157 "PEBS": "0", 7158 "Offcore": "1" 7159 }, 7160 { 7161 "EventCode": "0xB7", 7162 "UMask": "0x1", 7163 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE", 7164 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 7165 "PublicDescription": "Offcore demand data reads satisfied by a remote cache", 7166 "Counter": "2", 7167 "SampleAfterValue": "100000", 7168 "MSRIndex": "0x1A6", 7169 "MSRValue": "0x1801", 7170 "CounterMask": "0", 7171 "Invert": "0", 7172 "AnyThread": "0", 7173 "EdgeDetect": "0", 7174 "PEBS": "0", 7175 "Offcore": "1" 7176 }, 7177 { 7178 "EventCode": "0xB7", 7179 "UMask": "0x1", 7180 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 7181 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 7182 "PublicDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 7183 "Counter": "2", 7184 "SampleAfterValue": "100000", 7185 "MSRIndex": "0x1A6", 7186 "MSRValue": "0x3801", 7187 "CounterMask": "0", 7188 "Invert": "0", 7189 "AnyThread": "0", 7190 "EdgeDetect": "0", 7191 "PEBS": "0", 7192 "Offcore": "1" 7193 }, 7194 { 7195 "EventCode": "0xB7", 7196 "UMask": "0x1", 7197 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 7198 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 7199 "PublicDescription": "Offcore demand data reads that HIT in a remote cache", 7200 "Counter": "2", 7201 "SampleAfterValue": "100000", 7202 "MSRIndex": "0x1A6", 7203 "MSRValue": "0x1001", 7204 "CounterMask": "0", 7205 "Invert": "0", 7206 "AnyThread": "0", 7207 "EdgeDetect": "0", 7208 "PEBS": "0", 7209 "Offcore": "1" 7210 }, 7211 { 7212 "EventCode": "0xB7", 7213 "UMask": "0x1", 7214 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 7215 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 7216 "PublicDescription": "Offcore demand data reads that HITM in a remote cache", 7217 "Counter": "2", 7218 "SampleAfterValue": "100000", 7219 "MSRIndex": "0x1A6", 7220 "MSRValue": "0x801", 7221 "CounterMask": "0", 7222 "Invert": "0", 7223 "AnyThread": "0", 7224 "EdgeDetect": "0", 7225 "PEBS": "0", 7226 "Offcore": "1" 7227 }, 7228 { 7229 "EventCode": "0xB7", 7230 "UMask": "0x1", 7231 "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM", 7232 "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", 7233 "PublicDescription": "Offcore demand data reads satisfied by a remote DRAM", 7234 "Counter": "2", 7235 "SampleAfterValue": "100000", 7236 "MSRIndex": "0x1A6", 7237 "MSRValue": "0x2001", 7238 "CounterMask": "0", 7239 "Invert": "0", 7240 "AnyThread": "0", 7241 "EdgeDetect": "0", 7242 "PEBS": "0", 7243 "Offcore": "1" 7244 }, 7245 { 7246 "EventCode": "0xB7", 7247 "UMask": "0x1", 7248 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM", 7249 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 7250 "PublicDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 7251 "Counter": "2", 7252 "SampleAfterValue": "100000", 7253 "MSRIndex": "0x1A6", 7254 "MSRValue": "0x7F04", 7255 "CounterMask": "0", 7256 "Invert": "0", 7257 "AnyThread": "0", 7258 "EdgeDetect": "0", 7259 "PEBS": "0", 7260 "Offcore": "1" 7261 }, 7262 { 7263 "EventCode": "0xB7", 7264 "UMask": "0x1", 7265 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM", 7266 "BriefDescription": "Offcore demand code reads satisfied by any DRAM", 7267 "PublicDescription": "Offcore demand code reads satisfied by any DRAM", 7268 "Counter": "2", 7269 "SampleAfterValue": "100000", 7270 "MSRIndex": "0x1A6", 7271 "MSRValue": "0x6004", 7272 "CounterMask": "0", 7273 "Invert": "0", 7274 "AnyThread": "0", 7275 "EdgeDetect": "0", 7276 "PEBS": "0", 7277 "Offcore": "1" 7278 }, 7279 { 7280 "EventCode": "0xB7", 7281 "UMask": "0x1", 7282 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS", 7283 "BriefDescription": "Offcore demand code reads that missed the LLC", 7284 "PublicDescription": "Offcore demand code reads that missed the LLC", 7285 "Counter": "2", 7286 "SampleAfterValue": "100000", 7287 "MSRIndex": "0x1A6", 7288 "MSRValue": "0xF804", 7289 "CounterMask": "0", 7290 "Invert": "0", 7291 "AnyThread": "0", 7292 "EdgeDetect": "0", 7293 "PEBS": "0", 7294 "Offcore": "1" 7295 }, 7296 { 7297 "EventCode": "0xB7", 7298 "UMask": "0x1", 7299 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION", 7300 "BriefDescription": "All offcore demand code reads", 7301 "PublicDescription": "All offcore demand code reads", 7302 "Counter": "2", 7303 "SampleAfterValue": "100000", 7304 "MSRIndex": "0x1A6", 7305 "MSRValue": "0xFF04", 7306 "CounterMask": "0", 7307 "Invert": "0", 7308 "AnyThread": "0", 7309 "EdgeDetect": "0", 7310 "PEBS": "0", 7311 "Offcore": "1" 7312 }, 7313 { 7314 "EventCode": "0xB7", 7315 "UMask": "0x1", 7316 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO", 7317 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 7318 "PublicDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 7319 "Counter": "2", 7320 "SampleAfterValue": "100000", 7321 "MSRIndex": "0x1A6", 7322 "MSRValue": "0x8004", 7323 "CounterMask": "0", 7324 "Invert": "0", 7325 "AnyThread": "0", 7326 "EdgeDetect": "0", 7327 "PEBS": "0", 7328 "Offcore": "1" 7329 }, 7330 { 7331 "EventCode": "0xB7", 7332 "UMask": "0x1", 7333 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 7334 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 7335 "PublicDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 7336 "Counter": "2", 7337 "SampleAfterValue": "100000", 7338 "MSRIndex": "0x1A6", 7339 "MSRValue": "0x104", 7340 "CounterMask": "0", 7341 "Invert": "0", 7342 "AnyThread": "0", 7343 "EdgeDetect": "0", 7344 "PEBS": "0", 7345 "Offcore": "1" 7346 }, 7347 { 7348 "EventCode": "0xB7", 7349 "UMask": "0x1", 7350 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 7351 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 7352 "PublicDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 7353 "Counter": "2", 7354 "SampleAfterValue": "100000", 7355 "MSRIndex": "0x1A6", 7356 "MSRValue": "0x204", 7357 "CounterMask": "0", 7358 "Invert": "0", 7359 "AnyThread": "0", 7360 "EdgeDetect": "0", 7361 "PEBS": "0", 7362 "Offcore": "1" 7363 }, 7364 { 7365 "EventCode": "0xB7", 7366 "UMask": "0x1", 7367 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 7368 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 7369 "PublicDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 7370 "Counter": "2", 7371 "SampleAfterValue": "100000", 7372 "MSRIndex": "0x1A6", 7373 "MSRValue": "0x404", 7374 "CounterMask": "0", 7375 "Invert": "0", 7376 "AnyThread": "0", 7377 "EdgeDetect": "0", 7378 "PEBS": "0", 7379 "Offcore": "1" 7380 }, 7381 { 7382 "EventCode": "0xB7", 7383 "UMask": "0x1", 7384 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE", 7385 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 7386 "PublicDescription": "Offcore demand code reads satisfied by the LLC", 7387 "Counter": "2", 7388 "SampleAfterValue": "100000", 7389 "MSRIndex": "0x1A6", 7390 "MSRValue": "0x704", 7391 "CounterMask": "0", 7392 "Invert": "0", 7393 "AnyThread": "0", 7394 "EdgeDetect": "0", 7395 "PEBS": "0", 7396 "Offcore": "1" 7397 }, 7398 { 7399 "EventCode": "0xB7", 7400 "UMask": "0x1", 7401 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 7402 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 7403 "PublicDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 7404 "Counter": "2", 7405 "SampleAfterValue": "100000", 7406 "MSRIndex": "0x1A6", 7407 "MSRValue": "0x4704", 7408 "CounterMask": "0", 7409 "Invert": "0", 7410 "AnyThread": "0", 7411 "EdgeDetect": "0", 7412 "PEBS": "0", 7413 "Offcore": "1" 7414 }, 7415 { 7416 "EventCode": "0xB7", 7417 "UMask": "0x1", 7418 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM", 7419 "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", 7420 "PublicDescription": "Offcore demand code reads satisfied by the local DRAM", 7421 "Counter": "2", 7422 "SampleAfterValue": "100000", 7423 "MSRIndex": "0x1A6", 7424 "MSRValue": "0x4004", 7425 "CounterMask": "0", 7426 "Invert": "0", 7427 "AnyThread": "0", 7428 "EdgeDetect": "0", 7429 "PEBS": "0", 7430 "Offcore": "1" 7431 }, 7432 { 7433 "EventCode": "0xB7", 7434 "UMask": "0x1", 7435 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE", 7436 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 7437 "PublicDescription": "Offcore demand code reads satisfied by a remote cache", 7438 "Counter": "2", 7439 "SampleAfterValue": "100000", 7440 "MSRIndex": "0x1A6", 7441 "MSRValue": "0x1804", 7442 "CounterMask": "0", 7443 "Invert": "0", 7444 "AnyThread": "0", 7445 "EdgeDetect": "0", 7446 "PEBS": "0", 7447 "Offcore": "1" 7448 }, 7449 { 7450 "EventCode": "0xB7", 7451 "UMask": "0x1", 7452 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 7453 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 7454 "PublicDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 7455 "Counter": "2", 7456 "SampleAfterValue": "100000", 7457 "MSRIndex": "0x1A6", 7458 "MSRValue": "0x3804", 7459 "CounterMask": "0", 7460 "Invert": "0", 7461 "AnyThread": "0", 7462 "EdgeDetect": "0", 7463 "PEBS": "0", 7464 "Offcore": "1" 7465 }, 7466 { 7467 "EventCode": "0xB7", 7468 "UMask": "0x1", 7469 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT", 7470 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 7471 "PublicDescription": "Offcore demand code reads that HIT in a remote cache", 7472 "Counter": "2", 7473 "SampleAfterValue": "100000", 7474 "MSRIndex": "0x1A6", 7475 "MSRValue": "0x1004", 7476 "CounterMask": "0", 7477 "Invert": "0", 7478 "AnyThread": "0", 7479 "EdgeDetect": "0", 7480 "PEBS": "0", 7481 "Offcore": "1" 7482 }, 7483 { 7484 "EventCode": "0xB7", 7485 "UMask": "0x1", 7486 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM", 7487 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 7488 "PublicDescription": "Offcore demand code reads that HITM in a remote cache", 7489 "Counter": "2", 7490 "SampleAfterValue": "100000", 7491 "MSRIndex": "0x1A6", 7492 "MSRValue": "0x804", 7493 "CounterMask": "0", 7494 "Invert": "0", 7495 "AnyThread": "0", 7496 "EdgeDetect": "0", 7497 "PEBS": "0", 7498 "Offcore": "1" 7499 }, 7500 { 7501 "EventCode": "0xB7", 7502 "UMask": "0x1", 7503 "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM", 7504 "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", 7505 "PublicDescription": "Offcore demand code reads satisfied by a remote DRAM", 7506 "Counter": "2", 7507 "SampleAfterValue": "100000", 7508 "MSRIndex": "0x1A6", 7509 "MSRValue": "0x2004", 7510 "CounterMask": "0", 7511 "Invert": "0", 7512 "AnyThread": "0", 7513 "EdgeDetect": "0", 7514 "PEBS": "0", 7515 "Offcore": "1" 7516 }, 7517 { 7518 "EventCode": "0xB7", 7519 "UMask": "0x1", 7520 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM", 7521 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 7522 "PublicDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 7523 "Counter": "2", 7524 "SampleAfterValue": "100000", 7525 "MSRIndex": "0x1A6", 7526 "MSRValue": "0x7F02", 7527 "CounterMask": "0", 7528 "Invert": "0", 7529 "AnyThread": "0", 7530 "EdgeDetect": "0", 7531 "PEBS": "0", 7532 "Offcore": "1" 7533 }, 7534 { 7535 "EventCode": "0xB7", 7536 "UMask": "0x1", 7537 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM", 7538 "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", 7539 "PublicDescription": "Offcore demand RFO requests satisfied by any DRAM", 7540 "Counter": "2", 7541 "SampleAfterValue": "100000", 7542 "MSRIndex": "0x1A6", 7543 "MSRValue": "0x6002", 7544 "CounterMask": "0", 7545 "Invert": "0", 7546 "AnyThread": "0", 7547 "EdgeDetect": "0", 7548 "PEBS": "0", 7549 "Offcore": "1" 7550 }, 7551 { 7552 "EventCode": "0xB7", 7553 "UMask": "0x1", 7554 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS", 7555 "BriefDescription": "Offcore demand RFO requests that missed the LLC", 7556 "PublicDescription": "Offcore demand RFO requests that missed the LLC", 7557 "Counter": "2", 7558 "SampleAfterValue": "100000", 7559 "MSRIndex": "0x1A6", 7560 "MSRValue": "0xF802", 7561 "CounterMask": "0", 7562 "Invert": "0", 7563 "AnyThread": "0", 7564 "EdgeDetect": "0", 7565 "PEBS": "0", 7566 "Offcore": "1" 7567 }, 7568 { 7569 "EventCode": "0xB7", 7570 "UMask": "0x1", 7571 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION", 7572 "BriefDescription": "All offcore demand RFO requests", 7573 "PublicDescription": "All offcore demand RFO requests", 7574 "Counter": "2", 7575 "SampleAfterValue": "100000", 7576 "MSRIndex": "0x1A6", 7577 "MSRValue": "0xFF02", 7578 "CounterMask": "0", 7579 "Invert": "0", 7580 "AnyThread": "0", 7581 "EdgeDetect": "0", 7582 "PEBS": "0", 7583 "Offcore": "1" 7584 }, 7585 { 7586 "EventCode": "0xB7", 7587 "UMask": "0x1", 7588 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO", 7589 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 7590 "PublicDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 7591 "Counter": "2", 7592 "SampleAfterValue": "100000", 7593 "MSRIndex": "0x1A6", 7594 "MSRValue": "0x8002", 7595 "CounterMask": "0", 7596 "Invert": "0", 7597 "AnyThread": "0", 7598 "EdgeDetect": "0", 7599 "PEBS": "0", 7600 "Offcore": "1" 7601 }, 7602 { 7603 "EventCode": "0xB7", 7604 "UMask": "0x1", 7605 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 7606 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 7607 "PublicDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 7608 "Counter": "2", 7609 "SampleAfterValue": "100000", 7610 "MSRIndex": "0x1A6", 7611 "MSRValue": "0x102", 7612 "CounterMask": "0", 7613 "Invert": "0", 7614 "AnyThread": "0", 7615 "EdgeDetect": "0", 7616 "PEBS": "0", 7617 "Offcore": "1" 7618 }, 7619 { 7620 "EventCode": "0xB7", 7621 "UMask": "0x1", 7622 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 7623 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 7624 "PublicDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 7625 "Counter": "2", 7626 "SampleAfterValue": "100000", 7627 "MSRIndex": "0x1A6", 7628 "MSRValue": "0x202", 7629 "CounterMask": "0", 7630 "Invert": "0", 7631 "AnyThread": "0", 7632 "EdgeDetect": "0", 7633 "PEBS": "0", 7634 "Offcore": "1" 7635 }, 7636 { 7637 "EventCode": "0xB7", 7638 "UMask": "0x1", 7639 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 7640 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 7641 "PublicDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 7642 "Counter": "2", 7643 "SampleAfterValue": "100000", 7644 "MSRIndex": "0x1A6", 7645 "MSRValue": "0x402", 7646 "CounterMask": "0", 7647 "Invert": "0", 7648 "AnyThread": "0", 7649 "EdgeDetect": "0", 7650 "PEBS": "0", 7651 "Offcore": "1" 7652 }, 7653 { 7654 "EventCode": "0xB7", 7655 "UMask": "0x1", 7656 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE", 7657 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 7658 "PublicDescription": "Offcore demand RFO requests satisfied by the LLC", 7659 "Counter": "2", 7660 "SampleAfterValue": "100000", 7661 "MSRIndex": "0x1A6", 7662 "MSRValue": "0x702", 7663 "CounterMask": "0", 7664 "Invert": "0", 7665 "AnyThread": "0", 7666 "EdgeDetect": "0", 7667 "PEBS": "0", 7668 "Offcore": "1" 7669 }, 7670 { 7671 "EventCode": "0xB7", 7672 "UMask": "0x1", 7673 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM", 7674 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 7675 "PublicDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 7676 "Counter": "2", 7677 "SampleAfterValue": "100000", 7678 "MSRIndex": "0x1A6", 7679 "MSRValue": "0x4702", 7680 "CounterMask": "0", 7681 "Invert": "0", 7682 "AnyThread": "0", 7683 "EdgeDetect": "0", 7684 "PEBS": "0", 7685 "Offcore": "1" 7686 }, 7687 { 7688 "EventCode": "0xB7", 7689 "UMask": "0x1", 7690 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM", 7691 "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", 7692 "PublicDescription": "Offcore demand RFO requests satisfied by the local DRAM", 7693 "Counter": "2", 7694 "SampleAfterValue": "100000", 7695 "MSRIndex": "0x1A6", 7696 "MSRValue": "0x4002", 7697 "CounterMask": "0", 7698 "Invert": "0", 7699 "AnyThread": "0", 7700 "EdgeDetect": "0", 7701 "PEBS": "0", 7702 "Offcore": "1" 7703 }, 7704 { 7705 "EventCode": "0xB7", 7706 "UMask": "0x1", 7707 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE", 7708 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 7709 "PublicDescription": "Offcore demand RFO requests satisfied by a remote cache", 7710 "Counter": "2", 7711 "SampleAfterValue": "100000", 7712 "MSRIndex": "0x1A6", 7713 "MSRValue": "0x1802", 7714 "CounterMask": "0", 7715 "Invert": "0", 7716 "AnyThread": "0", 7717 "EdgeDetect": "0", 7718 "PEBS": "0", 7719 "Offcore": "1" 7720 }, 7721 { 7722 "EventCode": "0xB7", 7723 "UMask": "0x1", 7724 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM", 7725 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 7726 "PublicDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 7727 "Counter": "2", 7728 "SampleAfterValue": "100000", 7729 "MSRIndex": "0x1A6", 7730 "MSRValue": "0x3802", 7731 "CounterMask": "0", 7732 "Invert": "0", 7733 "AnyThread": "0", 7734 "EdgeDetect": "0", 7735 "PEBS": "0", 7736 "Offcore": "1" 7737 }, 7738 { 7739 "EventCode": "0xB7", 7740 "UMask": "0x1", 7741 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT", 7742 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 7743 "PublicDescription": "Offcore demand RFO requests that HIT in a remote cache", 7744 "Counter": "2", 7745 "SampleAfterValue": "100000", 7746 "MSRIndex": "0x1A6", 7747 "MSRValue": "0x1002", 7748 "CounterMask": "0", 7749 "Invert": "0", 7750 "AnyThread": "0", 7751 "EdgeDetect": "0", 7752 "PEBS": "0", 7753 "Offcore": "1" 7754 }, 7755 { 7756 "EventCode": "0xB7", 7757 "UMask": "0x1", 7758 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM", 7759 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 7760 "PublicDescription": "Offcore demand RFO requests that HITM in a remote cache", 7761 "Counter": "2", 7762 "SampleAfterValue": "100000", 7763 "MSRIndex": "0x1A6", 7764 "MSRValue": "0x802", 7765 "CounterMask": "0", 7766 "Invert": "0", 7767 "AnyThread": "0", 7768 "EdgeDetect": "0", 7769 "PEBS": "0", 7770 "Offcore": "1" 7771 }, 7772 { 7773 "EventCode": "0xB7", 7774 "UMask": "0x1", 7775 "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM", 7776 "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", 7777 "PublicDescription": "Offcore demand RFO requests satisfied by a remote DRAM", 7778 "Counter": "2", 7779 "SampleAfterValue": "100000", 7780 "MSRIndex": "0x1A6", 7781 "MSRValue": "0x2002", 7782 "CounterMask": "0", 7783 "Invert": "0", 7784 "AnyThread": "0", 7785 "EdgeDetect": "0", 7786 "PEBS": "0", 7787 "Offcore": "1" 7788 }, 7789 { 7790 "EventCode": "0xB7", 7791 "UMask": "0x1", 7792 "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM", 7793 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 7794 "PublicDescription": "Offcore other requests satisfied by any cache or DRAM.", 7795 "Counter": "2", 7796 "SampleAfterValue": "100000", 7797 "MSRIndex": "0x1A6", 7798 "MSRValue": "0x7F80", 7799 "CounterMask": "0", 7800 "Invert": "0", 7801 "AnyThread": "0", 7802 "EdgeDetect": "0", 7803 "PEBS": "0", 7804 "Offcore": "1" 7805 }, 7806 { 7807 "EventCode": "0xB7", 7808 "UMask": "0x1", 7809 "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_DRAM", 7810 "BriefDescription": "Offcore other requests satisfied by any DRAM", 7811 "PublicDescription": "Offcore other requests satisfied by any DRAM", 7812 "Counter": "2", 7813 "SampleAfterValue": "100000", 7814 "MSRIndex": "0x1A6", 7815 "MSRValue": "0x6080", 7816 "CounterMask": "0", 7817 "Invert": "0", 7818 "AnyThread": "0", 7819 "EdgeDetect": "0", 7820 "PEBS": "0", 7821 "Offcore": "1" 7822 }, 7823 { 7824 "EventCode": "0xB7", 7825 "UMask": "0x1", 7826 "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS", 7827 "BriefDescription": "Offcore other requests that missed the LLC", 7828 "PublicDescription": "Offcore other requests that missed the LLC", 7829 "Counter": "2", 7830 "SampleAfterValue": "100000", 7831 "MSRIndex": "0x1A6", 7832 "MSRValue": "0xF880", 7833 "CounterMask": "0", 7834 "Invert": "0", 7835 "AnyThread": "0", 7836 "EdgeDetect": "0", 7837 "PEBS": "0", 7838 "Offcore": "1" 7839 }, 7840 { 7841 "EventCode": "0xB7", 7842 "UMask": "0x1", 7843 "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION", 7844 "BriefDescription": "All offcore other requests", 7845 "PublicDescription": "All offcore other requests", 7846 "Counter": "2", 7847 "SampleAfterValue": "100000", 7848 "MSRIndex": "0x1A6", 7849 "MSRValue": "0xFF80", 7850 "CounterMask": "0", 7851 "Invert": "0", 7852 "AnyThread": "0", 7853 "EdgeDetect": "0", 7854 "PEBS": "0", 7855 "Offcore": "1" 7856 }, 7857 { 7858 "EventCode": "0xB7", 7859 "UMask": "0x1", 7860 "EventName": "OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO", 7861 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 7862 "PublicDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 7863 "Counter": "2", 7864 "SampleAfterValue": "100000", 7865 "MSRIndex": "0x1A6", 7866 "MSRValue": "0x8080", 7867 "CounterMask": "0", 7868 "Invert": "0", 7869 "AnyThread": "0", 7870 "EdgeDetect": "0", 7871 "PEBS": "0", 7872 "Offcore": "1" 7873 }, 7874 { 7875 "EventCode": "0xB7", 7876 "UMask": "0x1", 7877 "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE", 7878 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 7879 "PublicDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 7880 "Counter": "2", 7881 "SampleAfterValue": "100000", 7882 "MSRIndex": "0x1A6", 7883 "MSRValue": "0x180", 7884 "CounterMask": "0", 7885 "Invert": "0", 7886 "AnyThread": "0", 7887 "EdgeDetect": "0", 7888 "PEBS": "0", 7889 "Offcore": "1" 7890 }, 7891 { 7892 "EventCode": "0xB7", 7893 "UMask": "0x1", 7894 "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT", 7895 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 7896 "PublicDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 7897 "Counter": "2", 7898 "SampleAfterValue": "100000", 7899 "MSRIndex": "0x1A6", 7900 "MSRValue": "0x280", 7901 "CounterMask": "0", 7902 "Invert": "0", 7903 "AnyThread": "0", 7904 "EdgeDetect": "0", 7905 "PEBS": "0", 7906 "Offcore": "1" 7907 }, 7908 { 7909 "EventCode": "0xB7", 7910 "UMask": "0x1", 7911 "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM", 7912 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 7913 "PublicDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 7914 "Counter": "2", 7915 "SampleAfterValue": "100000", 7916 "MSRIndex": "0x1A6", 7917 "MSRValue": "0x480", 7918 "CounterMask": "0", 7919 "Invert": "0", 7920 "AnyThread": "0", 7921 "EdgeDetect": "0", 7922 "PEBS": "0", 7923 "Offcore": "1" 7924 }, 7925 { 7926 "EventCode": "0xB7", 7927 "UMask": "0x1", 7928 "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE", 7929 "BriefDescription": "Offcore other requests satisfied by the LLC", 7930 "PublicDescription": "Offcore other requests satisfied by the LLC", 7931 "Counter": "2", 7932 "SampleAfterValue": "100000", 7933 "MSRIndex": "0x1A6", 7934 "MSRValue": "0x780", 7935 "CounterMask": "0", 7936 "Invert": "0", 7937 "AnyThread": "0", 7938 "EdgeDetect": "0", 7939 "PEBS": "0", 7940 "Offcore": "1" 7941 }, 7942 { 7943 "EventCode": "0xB7", 7944 "UMask": "0x1", 7945 "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM", 7946 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 7947 "PublicDescription": "Offcore other requests satisfied by the LLC or local DRAM", 7948 "Counter": "2", 7949 "SampleAfterValue": "100000", 7950 "MSRIndex": "0x1A6", 7951 "MSRValue": "0x4780", 7952 "CounterMask": "0", 7953 "Invert": "0", 7954 "AnyThread": "0", 7955 "EdgeDetect": "0", 7956 "PEBS": "0", 7957 "Offcore": "1" 7958 }, 7959 { 7960 "EventCode": "0xB7", 7961 "UMask": "0x1", 7962 "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE", 7963 "BriefDescription": "Offcore other requests satisfied by a remote cache", 7964 "PublicDescription": "Offcore other requests satisfied by a remote cache", 7965 "Counter": "2", 7966 "SampleAfterValue": "100000", 7967 "MSRIndex": "0x1A6", 7968 "MSRValue": "0x1880", 7969 "CounterMask": "0", 7970 "Invert": "0", 7971 "AnyThread": "0", 7972 "EdgeDetect": "0", 7973 "PEBS": "0", 7974 "Offcore": "1" 7975 }, 7976 { 7977 "EventCode": "0xB7", 7978 "UMask": "0x1", 7979 "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM", 7980 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 7981 "PublicDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 7982 "Counter": "2", 7983 "SampleAfterValue": "100000", 7984 "MSRIndex": "0x1A6", 7985 "MSRValue": "0x3880", 7986 "CounterMask": "0", 7987 "Invert": "0", 7988 "AnyThread": "0", 7989 "EdgeDetect": "0", 7990 "PEBS": "0", 7991 "Offcore": "1" 7992 }, 7993 { 7994 "EventCode": "0xB7", 7995 "UMask": "0x1", 7996 "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT", 7997 "BriefDescription": "Offcore other requests that HIT in a remote cache", 7998 "PublicDescription": "Offcore other requests that HIT in a remote cache", 7999 "Counter": "2", 8000 "SampleAfterValue": "100000", 8001 "MSRIndex": "0x1A6", 8002 "MSRValue": "0x1080", 8003 "CounterMask": "0", 8004 "Invert": "0", 8005 "AnyThread": "0", 8006 "EdgeDetect": "0", 8007 "PEBS": "0", 8008 "Offcore": "1" 8009 }, 8010 { 8011 "EventCode": "0xB7", 8012 "UMask": "0x1", 8013 "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM", 8014 "BriefDescription": "Offcore other requests that HITM in a remote cache", 8015 "PublicDescription": "Offcore other requests that HITM in a remote cache", 8016 "Counter": "2", 8017 "SampleAfterValue": "100000", 8018 "MSRIndex": "0x1A6", 8019 "MSRValue": "0x880", 8020 "CounterMask": "0", 8021 "Invert": "0", 8022 "AnyThread": "0", 8023 "EdgeDetect": "0", 8024 "PEBS": "0", 8025 "Offcore": "1" 8026 }, 8027 { 8028 "EventCode": "0xB7", 8029 "UMask": "0x1", 8030 "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM", 8031 "BriefDescription": "Offcore other requests satisfied by a remote DRAM", 8032 "PublicDescription": "Offcore other requests satisfied by a remote DRAM", 8033 "Counter": "2", 8034 "SampleAfterValue": "100000", 8035 "MSRIndex": "0x1A6", 8036 "MSRValue": "0x2080", 8037 "CounterMask": "0", 8038 "Invert": "0", 8039 "AnyThread": "0", 8040 "EdgeDetect": "0", 8041 "PEBS": "0", 8042 "Offcore": "1" 8043 }, 8044 { 8045 "EventCode": "0xB7", 8046 "UMask": "0x1", 8047 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM", 8048 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 8049 "PublicDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 8050 "Counter": "2", 8051 "SampleAfterValue": "100000", 8052 "MSRIndex": "0x1A6", 8053 "MSRValue": "0x7F30", 8054 "CounterMask": "0", 8055 "Invert": "0", 8056 "AnyThread": "0", 8057 "EdgeDetect": "0", 8058 "PEBS": "0", 8059 "Offcore": "1" 8060 }, 8061 { 8062 "EventCode": "0xB7", 8063 "UMask": "0x1", 8064 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM", 8065 "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", 8066 "PublicDescription": "Offcore prefetch data requests satisfied by any DRAM", 8067 "Counter": "2", 8068 "SampleAfterValue": "100000", 8069 "MSRIndex": "0x1A6", 8070 "MSRValue": "0x6030", 8071 "CounterMask": "0", 8072 "Invert": "0", 8073 "AnyThread": "0", 8074 "EdgeDetect": "0", 8075 "PEBS": "0", 8076 "Offcore": "1" 8077 }, 8078 { 8079 "EventCode": "0xB7", 8080 "UMask": "0x1", 8081 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS", 8082 "BriefDescription": "Offcore prefetch data requests that missed the LLC", 8083 "PublicDescription": "Offcore prefetch data requests that missed the LLC", 8084 "Counter": "2", 8085 "SampleAfterValue": "100000", 8086 "MSRIndex": "0x1A6", 8087 "MSRValue": "0xF830", 8088 "CounterMask": "0", 8089 "Invert": "0", 8090 "AnyThread": "0", 8091 "EdgeDetect": "0", 8092 "PEBS": "0", 8093 "Offcore": "1" 8094 }, 8095 { 8096 "EventCode": "0xB7", 8097 "UMask": "0x1", 8098 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION", 8099 "BriefDescription": "All offcore prefetch data requests", 8100 "PublicDescription": "All offcore prefetch data requests", 8101 "Counter": "2", 8102 "SampleAfterValue": "100000", 8103 "MSRIndex": "0x1A6", 8104 "MSRValue": "0xFF30", 8105 "CounterMask": "0", 8106 "Invert": "0", 8107 "AnyThread": "0", 8108 "EdgeDetect": "0", 8109 "PEBS": "0", 8110 "Offcore": "1" 8111 }, 8112 { 8113 "EventCode": "0xB7", 8114 "UMask": "0x1", 8115 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO", 8116 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 8117 "PublicDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 8118 "Counter": "2", 8119 "SampleAfterValue": "100000", 8120 "MSRIndex": "0x1A6", 8121 "MSRValue": "0x8030", 8122 "CounterMask": "0", 8123 "Invert": "0", 8124 "AnyThread": "0", 8125 "EdgeDetect": "0", 8126 "PEBS": "0", 8127 "Offcore": "1" 8128 }, 8129 { 8130 "EventCode": "0xB7", 8131 "UMask": "0x1", 8132 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE", 8133 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 8134 "PublicDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 8135 "Counter": "2", 8136 "SampleAfterValue": "100000", 8137 "MSRIndex": "0x1A6", 8138 "MSRValue": "0x130", 8139 "CounterMask": "0", 8140 "Invert": "0", 8141 "AnyThread": "0", 8142 "EdgeDetect": "0", 8143 "PEBS": "0", 8144 "Offcore": "1" 8145 }, 8146 { 8147 "EventCode": "0xB7", 8148 "UMask": "0x1", 8149 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 8150 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 8151 "PublicDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 8152 "Counter": "2", 8153 "SampleAfterValue": "100000", 8154 "MSRIndex": "0x1A6", 8155 "MSRValue": "0x230", 8156 "CounterMask": "0", 8157 "Invert": "0", 8158 "AnyThread": "0", 8159 "EdgeDetect": "0", 8160 "PEBS": "0", 8161 "Offcore": "1" 8162 }, 8163 { 8164 "EventCode": "0xB7", 8165 "UMask": "0x1", 8166 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 8167 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 8168 "PublicDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 8169 "Counter": "2", 8170 "SampleAfterValue": "100000", 8171 "MSRIndex": "0x1A6", 8172 "MSRValue": "0x430", 8173 "CounterMask": "0", 8174 "Invert": "0", 8175 "AnyThread": "0", 8176 "EdgeDetect": "0", 8177 "PEBS": "0", 8178 "Offcore": "1" 8179 }, 8180 { 8181 "EventCode": "0xB7", 8182 "UMask": "0x1", 8183 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE", 8184 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 8185 "PublicDescription": "Offcore prefetch data requests satisfied by the LLC", 8186 "Counter": "2", 8187 "SampleAfterValue": "100000", 8188 "MSRIndex": "0x1A6", 8189 "MSRValue": "0x730", 8190 "CounterMask": "0", 8191 "Invert": "0", 8192 "AnyThread": "0", 8193 "EdgeDetect": "0", 8194 "PEBS": "0", 8195 "Offcore": "1" 8196 }, 8197 { 8198 "EventCode": "0xB7", 8199 "UMask": "0x1", 8200 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM", 8201 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 8202 "PublicDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 8203 "Counter": "2", 8204 "SampleAfterValue": "100000", 8205 "MSRIndex": "0x1A6", 8206 "MSRValue": "0x4730", 8207 "CounterMask": "0", 8208 "Invert": "0", 8209 "AnyThread": "0", 8210 "EdgeDetect": "0", 8211 "PEBS": "0", 8212 "Offcore": "1" 8213 }, 8214 { 8215 "EventCode": "0xB7", 8216 "UMask": "0x1", 8217 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM", 8218 "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", 8219 "PublicDescription": "Offcore prefetch data requests satisfied by the local DRAM", 8220 "Counter": "2", 8221 "SampleAfterValue": "100000", 8222 "MSRIndex": "0x1A6", 8223 "MSRValue": "0x4030", 8224 "CounterMask": "0", 8225 "Invert": "0", 8226 "AnyThread": "0", 8227 "EdgeDetect": "0", 8228 "PEBS": "0", 8229 "Offcore": "1" 8230 }, 8231 { 8232 "EventCode": "0xB7", 8233 "UMask": "0x1", 8234 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE", 8235 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 8236 "PublicDescription": "Offcore prefetch data requests satisfied by a remote cache", 8237 "Counter": "2", 8238 "SampleAfterValue": "100000", 8239 "MSRIndex": "0x1A6", 8240 "MSRValue": "0x1830", 8241 "CounterMask": "0", 8242 "Invert": "0", 8243 "AnyThread": "0", 8244 "EdgeDetect": "0", 8245 "PEBS": "0", 8246 "Offcore": "1" 8247 }, 8248 { 8249 "EventCode": "0xB7", 8250 "UMask": "0x1", 8251 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM", 8252 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 8253 "PublicDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 8254 "Counter": "2", 8255 "SampleAfterValue": "100000", 8256 "MSRIndex": "0x1A6", 8257 "MSRValue": "0x3830", 8258 "CounterMask": "0", 8259 "Invert": "0", 8260 "AnyThread": "0", 8261 "EdgeDetect": "0", 8262 "PEBS": "0", 8263 "Offcore": "1" 8264 }, 8265 { 8266 "EventCode": "0xB7", 8267 "UMask": "0x1", 8268 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT", 8269 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 8270 "PublicDescription": "Offcore prefetch data requests that HIT in a remote cache", 8271 "Counter": "2", 8272 "SampleAfterValue": "100000", 8273 "MSRIndex": "0x1A6", 8274 "MSRValue": "0x1030", 8275 "CounterMask": "0", 8276 "Invert": "0", 8277 "AnyThread": "0", 8278 "EdgeDetect": "0", 8279 "PEBS": "0", 8280 "Offcore": "1" 8281 }, 8282 { 8283 "EventCode": "0xB7", 8284 "UMask": "0x1", 8285 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM", 8286 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 8287 "PublicDescription": "Offcore prefetch data requests that HITM in a remote cache", 8288 "Counter": "2", 8289 "SampleAfterValue": "100000", 8290 "MSRIndex": "0x1A6", 8291 "MSRValue": "0x830", 8292 "CounterMask": "0", 8293 "Invert": "0", 8294 "AnyThread": "0", 8295 "EdgeDetect": "0", 8296 "PEBS": "0", 8297 "Offcore": "1" 8298 }, 8299 { 8300 "EventCode": "0xB7", 8301 "UMask": "0x1", 8302 "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM", 8303 "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", 8304 "PublicDescription": "Offcore prefetch data requests satisfied by a remote DRAM", 8305 "Counter": "2", 8306 "SampleAfterValue": "100000", 8307 "MSRIndex": "0x1A6", 8308 "MSRValue": "0x2030", 8309 "CounterMask": "0", 8310 "Invert": "0", 8311 "AnyThread": "0", 8312 "EdgeDetect": "0", 8313 "PEBS": "0", 8314 "Offcore": "1" 8315 }, 8316 { 8317 "EventCode": "0xB7", 8318 "UMask": "0x1", 8319 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM", 8320 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 8321 "PublicDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 8322 "Counter": "2", 8323 "SampleAfterValue": "100000", 8324 "MSRIndex": "0x1A6", 8325 "MSRValue": "0x7F10", 8326 "CounterMask": "0", 8327 "Invert": "0", 8328 "AnyThread": "0", 8329 "EdgeDetect": "0", 8330 "PEBS": "0", 8331 "Offcore": "1" 8332 }, 8333 { 8334 "EventCode": "0xB7", 8335 "UMask": "0x1", 8336 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM", 8337 "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", 8338 "PublicDescription": "Offcore prefetch data reads satisfied by any DRAM", 8339 "Counter": "2", 8340 "SampleAfterValue": "100000", 8341 "MSRIndex": "0x1A6", 8342 "MSRValue": "0x6010", 8343 "CounterMask": "0", 8344 "Invert": "0", 8345 "AnyThread": "0", 8346 "EdgeDetect": "0", 8347 "PEBS": "0", 8348 "Offcore": "1" 8349 }, 8350 { 8351 "EventCode": "0xB7", 8352 "UMask": "0x1", 8353 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS", 8354 "BriefDescription": "Offcore prefetch data reads that missed the LLC", 8355 "PublicDescription": "Offcore prefetch data reads that missed the LLC", 8356 "Counter": "2", 8357 "SampleAfterValue": "100000", 8358 "MSRIndex": "0x1A6", 8359 "MSRValue": "0xF810", 8360 "CounterMask": "0", 8361 "Invert": "0", 8362 "AnyThread": "0", 8363 "EdgeDetect": "0", 8364 "PEBS": "0", 8365 "Offcore": "1" 8366 }, 8367 { 8368 "EventCode": "0xB7", 8369 "UMask": "0x1", 8370 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION", 8371 "BriefDescription": "All offcore prefetch data reads", 8372 "PublicDescription": "All offcore prefetch data reads", 8373 "Counter": "2", 8374 "SampleAfterValue": "100000", 8375 "MSRIndex": "0x1A6", 8376 "MSRValue": "0xFF10", 8377 "CounterMask": "0", 8378 "Invert": "0", 8379 "AnyThread": "0", 8380 "EdgeDetect": "0", 8381 "PEBS": "0", 8382 "Offcore": "1" 8383 }, 8384 { 8385 "EventCode": "0xB7", 8386 "UMask": "0x1", 8387 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO", 8388 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 8389 "PublicDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 8390 "Counter": "2", 8391 "SampleAfterValue": "100000", 8392 "MSRIndex": "0x1A6", 8393 "MSRValue": "0x8010", 8394 "CounterMask": "0", 8395 "Invert": "0", 8396 "AnyThread": "0", 8397 "EdgeDetect": "0", 8398 "PEBS": "0", 8399 "Offcore": "1" 8400 }, 8401 { 8402 "EventCode": "0xB7", 8403 "UMask": "0x1", 8404 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 8405 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 8406 "PublicDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 8407 "Counter": "2", 8408 "SampleAfterValue": "100000", 8409 "MSRIndex": "0x1A6", 8410 "MSRValue": "0x110", 8411 "CounterMask": "0", 8412 "Invert": "0", 8413 "AnyThread": "0", 8414 "EdgeDetect": "0", 8415 "PEBS": "0", 8416 "Offcore": "1" 8417 }, 8418 { 8419 "EventCode": "0xB7", 8420 "UMask": "0x1", 8421 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 8422 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 8423 "PublicDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 8424 "Counter": "2", 8425 "SampleAfterValue": "100000", 8426 "MSRIndex": "0x1A6", 8427 "MSRValue": "0x210", 8428 "CounterMask": "0", 8429 "Invert": "0", 8430 "AnyThread": "0", 8431 "EdgeDetect": "0", 8432 "PEBS": "0", 8433 "Offcore": "1" 8434 }, 8435 { 8436 "EventCode": "0xB7", 8437 "UMask": "0x1", 8438 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 8439 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 8440 "PublicDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 8441 "Counter": "2", 8442 "SampleAfterValue": "100000", 8443 "MSRIndex": "0x1A6", 8444 "MSRValue": "0x410", 8445 "CounterMask": "0", 8446 "Invert": "0", 8447 "AnyThread": "0", 8448 "EdgeDetect": "0", 8449 "PEBS": "0", 8450 "Offcore": "1" 8451 }, 8452 { 8453 "EventCode": "0xB7", 8454 "UMask": "0x1", 8455 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE", 8456 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 8457 "PublicDescription": "Offcore prefetch data reads satisfied by the LLC", 8458 "Counter": "2", 8459 "SampleAfterValue": "100000", 8460 "MSRIndex": "0x1A6", 8461 "MSRValue": "0x710", 8462 "CounterMask": "0", 8463 "Invert": "0", 8464 "AnyThread": "0", 8465 "EdgeDetect": "0", 8466 "PEBS": "0", 8467 "Offcore": "1" 8468 }, 8469 { 8470 "EventCode": "0xB7", 8471 "UMask": "0x1", 8472 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM", 8473 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 8474 "PublicDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 8475 "Counter": "2", 8476 "SampleAfterValue": "100000", 8477 "MSRIndex": "0x1A6", 8478 "MSRValue": "0x4710", 8479 "CounterMask": "0", 8480 "Invert": "0", 8481 "AnyThread": "0", 8482 "EdgeDetect": "0", 8483 "PEBS": "0", 8484 "Offcore": "1" 8485 }, 8486 { 8487 "EventCode": "0xB7", 8488 "UMask": "0x1", 8489 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM", 8490 "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", 8491 "PublicDescription": "Offcore prefetch data reads satisfied by the local DRAM", 8492 "Counter": "2", 8493 "SampleAfterValue": "100000", 8494 "MSRIndex": "0x1A6", 8495 "MSRValue": "0x4010", 8496 "CounterMask": "0", 8497 "Invert": "0", 8498 "AnyThread": "0", 8499 "EdgeDetect": "0", 8500 "PEBS": "0", 8501 "Offcore": "1" 8502 }, 8503 { 8504 "EventCode": "0xB7", 8505 "UMask": "0x1", 8506 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE", 8507 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 8508 "PublicDescription": "Offcore prefetch data reads satisfied by a remote cache", 8509 "Counter": "2", 8510 "SampleAfterValue": "100000", 8511 "MSRIndex": "0x1A6", 8512 "MSRValue": "0x1810", 8513 "CounterMask": "0", 8514 "Invert": "0", 8515 "AnyThread": "0", 8516 "EdgeDetect": "0", 8517 "PEBS": "0", 8518 "Offcore": "1" 8519 }, 8520 { 8521 "EventCode": "0xB7", 8522 "UMask": "0x1", 8523 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM", 8524 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 8525 "PublicDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 8526 "Counter": "2", 8527 "SampleAfterValue": "100000", 8528 "MSRIndex": "0x1A6", 8529 "MSRValue": "0x3810", 8530 "CounterMask": "0", 8531 "Invert": "0", 8532 "AnyThread": "0", 8533 "EdgeDetect": "0", 8534 "PEBS": "0", 8535 "Offcore": "1" 8536 }, 8537 { 8538 "EventCode": "0xB7", 8539 "UMask": "0x1", 8540 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT", 8541 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 8542 "PublicDescription": "Offcore prefetch data reads that HIT in a remote cache", 8543 "Counter": "2", 8544 "SampleAfterValue": "100000", 8545 "MSRIndex": "0x1A6", 8546 "MSRValue": "0x1010", 8547 "CounterMask": "0", 8548 "Invert": "0", 8549 "AnyThread": "0", 8550 "EdgeDetect": "0", 8551 "PEBS": "0", 8552 "Offcore": "1" 8553 }, 8554 { 8555 "EventCode": "0xB7", 8556 "UMask": "0x1", 8557 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM", 8558 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 8559 "PublicDescription": "Offcore prefetch data reads that HITM in a remote cache", 8560 "Counter": "2", 8561 "SampleAfterValue": "100000", 8562 "MSRIndex": "0x1A6", 8563 "MSRValue": "0x810", 8564 "CounterMask": "0", 8565 "Invert": "0", 8566 "AnyThread": "0", 8567 "EdgeDetect": "0", 8568 "PEBS": "0", 8569 "Offcore": "1" 8570 }, 8571 { 8572 "EventCode": "0xB7", 8573 "UMask": "0x1", 8574 "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM", 8575 "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", 8576 "PublicDescription": "Offcore prefetch data reads satisfied by a remote DRAM", 8577 "Counter": "2", 8578 "SampleAfterValue": "100000", 8579 "MSRIndex": "0x1A6", 8580 "MSRValue": "0x2010", 8581 "CounterMask": "0", 8582 "Invert": "0", 8583 "AnyThread": "0", 8584 "EdgeDetect": "0", 8585 "PEBS": "0", 8586 "Offcore": "1" 8587 }, 8588 { 8589 "EventCode": "0xB7", 8590 "UMask": "0x1", 8591 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM", 8592 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 8593 "PublicDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 8594 "Counter": "2", 8595 "SampleAfterValue": "100000", 8596 "MSRIndex": "0x1A6", 8597 "MSRValue": "0x7F40", 8598 "CounterMask": "0", 8599 "Invert": "0", 8600 "AnyThread": "0", 8601 "EdgeDetect": "0", 8602 "PEBS": "0", 8603 "Offcore": "1" 8604 }, 8605 { 8606 "EventCode": "0xB7", 8607 "UMask": "0x1", 8608 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM", 8609 "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", 8610 "PublicDescription": "Offcore prefetch code reads satisfied by any DRAM", 8611 "Counter": "2", 8612 "SampleAfterValue": "100000", 8613 "MSRIndex": "0x1A6", 8614 "MSRValue": "0x6040", 8615 "CounterMask": "0", 8616 "Invert": "0", 8617 "AnyThread": "0", 8618 "EdgeDetect": "0", 8619 "PEBS": "0", 8620 "Offcore": "1" 8621 }, 8622 { 8623 "EventCode": "0xB7", 8624 "UMask": "0x1", 8625 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS", 8626 "BriefDescription": "Offcore prefetch code reads that missed the LLC", 8627 "PublicDescription": "Offcore prefetch code reads that missed the LLC", 8628 "Counter": "2", 8629 "SampleAfterValue": "100000", 8630 "MSRIndex": "0x1A6", 8631 "MSRValue": "0xF840", 8632 "CounterMask": "0", 8633 "Invert": "0", 8634 "AnyThread": "0", 8635 "EdgeDetect": "0", 8636 "PEBS": "0", 8637 "Offcore": "1" 8638 }, 8639 { 8640 "EventCode": "0xB7", 8641 "UMask": "0x1", 8642 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION", 8643 "BriefDescription": "All offcore prefetch code reads", 8644 "PublicDescription": "All offcore prefetch code reads", 8645 "Counter": "2", 8646 "SampleAfterValue": "100000", 8647 "MSRIndex": "0x1A6", 8648 "MSRValue": "0xFF40", 8649 "CounterMask": "0", 8650 "Invert": "0", 8651 "AnyThread": "0", 8652 "EdgeDetect": "0", 8653 "PEBS": "0", 8654 "Offcore": "1" 8655 }, 8656 { 8657 "EventCode": "0xB7", 8658 "UMask": "0x1", 8659 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO", 8660 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 8661 "PublicDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 8662 "Counter": "2", 8663 "SampleAfterValue": "100000", 8664 "MSRIndex": "0x1A6", 8665 "MSRValue": "0x8040", 8666 "CounterMask": "0", 8667 "Invert": "0", 8668 "AnyThread": "0", 8669 "EdgeDetect": "0", 8670 "PEBS": "0", 8671 "Offcore": "1" 8672 }, 8673 { 8674 "EventCode": "0xB7", 8675 "UMask": "0x1", 8676 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 8677 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 8678 "PublicDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 8679 "Counter": "2", 8680 "SampleAfterValue": "100000", 8681 "MSRIndex": "0x1A6", 8682 "MSRValue": "0x140", 8683 "CounterMask": "0", 8684 "Invert": "0", 8685 "AnyThread": "0", 8686 "EdgeDetect": "0", 8687 "PEBS": "0", 8688 "Offcore": "1" 8689 }, 8690 { 8691 "EventCode": "0xB7", 8692 "UMask": "0x1", 8693 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 8694 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 8695 "PublicDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 8696 "Counter": "2", 8697 "SampleAfterValue": "100000", 8698 "MSRIndex": "0x1A6", 8699 "MSRValue": "0x240", 8700 "CounterMask": "0", 8701 "Invert": "0", 8702 "AnyThread": "0", 8703 "EdgeDetect": "0", 8704 "PEBS": "0", 8705 "Offcore": "1" 8706 }, 8707 { 8708 "EventCode": "0xB7", 8709 "UMask": "0x1", 8710 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 8711 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 8712 "PublicDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 8713 "Counter": "2", 8714 "SampleAfterValue": "100000", 8715 "MSRIndex": "0x1A6", 8716 "MSRValue": "0x440", 8717 "CounterMask": "0", 8718 "Invert": "0", 8719 "AnyThread": "0", 8720 "EdgeDetect": "0", 8721 "PEBS": "0", 8722 "Offcore": "1" 8723 }, 8724 { 8725 "EventCode": "0xB7", 8726 "UMask": "0x1", 8727 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE", 8728 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 8729 "PublicDescription": "Offcore prefetch code reads satisfied by the LLC", 8730 "Counter": "2", 8731 "SampleAfterValue": "100000", 8732 "MSRIndex": "0x1A6", 8733 "MSRValue": "0x740", 8734 "CounterMask": "0", 8735 "Invert": "0", 8736 "AnyThread": "0", 8737 "EdgeDetect": "0", 8738 "PEBS": "0", 8739 "Offcore": "1" 8740 }, 8741 { 8742 "EventCode": "0xB7", 8743 "UMask": "0x1", 8744 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM", 8745 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 8746 "PublicDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 8747 "Counter": "2", 8748 "SampleAfterValue": "100000", 8749 "MSRIndex": "0x1A6", 8750 "MSRValue": "0x4740", 8751 "CounterMask": "0", 8752 "Invert": "0", 8753 "AnyThread": "0", 8754 "EdgeDetect": "0", 8755 "PEBS": "0", 8756 "Offcore": "1" 8757 }, 8758 { 8759 "EventCode": "0xB7", 8760 "UMask": "0x1", 8761 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM", 8762 "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", 8763 "PublicDescription": "Offcore prefetch code reads satisfied by the local DRAM", 8764 "Counter": "2", 8765 "SampleAfterValue": "100000", 8766 "MSRIndex": "0x1A6", 8767 "MSRValue": "0x4040", 8768 "CounterMask": "0", 8769 "Invert": "0", 8770 "AnyThread": "0", 8771 "EdgeDetect": "0", 8772 "PEBS": "0", 8773 "Offcore": "1" 8774 }, 8775 { 8776 "EventCode": "0xB7", 8777 "UMask": "0x1", 8778 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE", 8779 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 8780 "PublicDescription": "Offcore prefetch code reads satisfied by a remote cache", 8781 "Counter": "2", 8782 "SampleAfterValue": "100000", 8783 "MSRIndex": "0x1A6", 8784 "MSRValue": "0x1840", 8785 "CounterMask": "0", 8786 "Invert": "0", 8787 "AnyThread": "0", 8788 "EdgeDetect": "0", 8789 "PEBS": "0", 8790 "Offcore": "1" 8791 }, 8792 { 8793 "EventCode": "0xB7", 8794 "UMask": "0x1", 8795 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM", 8796 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 8797 "PublicDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 8798 "Counter": "2", 8799 "SampleAfterValue": "100000", 8800 "MSRIndex": "0x1A6", 8801 "MSRValue": "0x3840", 8802 "CounterMask": "0", 8803 "Invert": "0", 8804 "AnyThread": "0", 8805 "EdgeDetect": "0", 8806 "PEBS": "0", 8807 "Offcore": "1" 8808 }, 8809 { 8810 "EventCode": "0xB7", 8811 "UMask": "0x1", 8812 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT", 8813 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 8814 "PublicDescription": "Offcore prefetch code reads that HIT in a remote cache", 8815 "Counter": "2", 8816 "SampleAfterValue": "100000", 8817 "MSRIndex": "0x1A6", 8818 "MSRValue": "0x1040", 8819 "CounterMask": "0", 8820 "Invert": "0", 8821 "AnyThread": "0", 8822 "EdgeDetect": "0", 8823 "PEBS": "0", 8824 "Offcore": "1" 8825 }, 8826 { 8827 "EventCode": "0xB7", 8828 "UMask": "0x1", 8829 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM", 8830 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 8831 "PublicDescription": "Offcore prefetch code reads that HITM in a remote cache", 8832 "Counter": "2", 8833 "SampleAfterValue": "100000", 8834 "MSRIndex": "0x1A6", 8835 "MSRValue": "0x840", 8836 "CounterMask": "0", 8837 "Invert": "0", 8838 "AnyThread": "0", 8839 "EdgeDetect": "0", 8840 "PEBS": "0", 8841 "Offcore": "1" 8842 }, 8843 { 8844 "EventCode": "0xB7", 8845 "UMask": "0x1", 8846 "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM", 8847 "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", 8848 "PublicDescription": "Offcore prefetch code reads satisfied by a remote DRAM", 8849 "Counter": "2", 8850 "SampleAfterValue": "100000", 8851 "MSRIndex": "0x1A6", 8852 "MSRValue": "0x2040", 8853 "CounterMask": "0", 8854 "Invert": "0", 8855 "AnyThread": "0", 8856 "EdgeDetect": "0", 8857 "PEBS": "0", 8858 "Offcore": "1" 8859 }, 8860 { 8861 "EventCode": "0xB7", 8862 "UMask": "0x1", 8863 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM", 8864 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 8865 "PublicDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 8866 "Counter": "2", 8867 "SampleAfterValue": "100000", 8868 "MSRIndex": "0x1A6", 8869 "MSRValue": "0x7F20", 8870 "CounterMask": "0", 8871 "Invert": "0", 8872 "AnyThread": "0", 8873 "EdgeDetect": "0", 8874 "PEBS": "0", 8875 "Offcore": "1" 8876 }, 8877 { 8878 "EventCode": "0xB7", 8879 "UMask": "0x1", 8880 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM", 8881 "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", 8882 "PublicDescription": "Offcore prefetch RFO requests satisfied by any DRAM", 8883 "Counter": "2", 8884 "SampleAfterValue": "100000", 8885 "MSRIndex": "0x1A6", 8886 "MSRValue": "0x6020", 8887 "CounterMask": "0", 8888 "Invert": "0", 8889 "AnyThread": "0", 8890 "EdgeDetect": "0", 8891 "PEBS": "0", 8892 "Offcore": "1" 8893 }, 8894 { 8895 "EventCode": "0xB7", 8896 "UMask": "0x1", 8897 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS", 8898 "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", 8899 "PublicDescription": "Offcore prefetch RFO requests that missed the LLC", 8900 "Counter": "2", 8901 "SampleAfterValue": "100000", 8902 "MSRIndex": "0x1A6", 8903 "MSRValue": "0xF820", 8904 "CounterMask": "0", 8905 "Invert": "0", 8906 "AnyThread": "0", 8907 "EdgeDetect": "0", 8908 "PEBS": "0", 8909 "Offcore": "1" 8910 }, 8911 { 8912 "EventCode": "0xB7", 8913 "UMask": "0x1", 8914 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION", 8915 "BriefDescription": "All offcore prefetch RFO requests", 8916 "PublicDescription": "All offcore prefetch RFO requests", 8917 "Counter": "2", 8918 "SampleAfterValue": "100000", 8919 "MSRIndex": "0x1A6", 8920 "MSRValue": "0xFF20", 8921 "CounterMask": "0", 8922 "Invert": "0", 8923 "AnyThread": "0", 8924 "EdgeDetect": "0", 8925 "PEBS": "0", 8926 "Offcore": "1" 8927 }, 8928 { 8929 "EventCode": "0xB7", 8930 "UMask": "0x1", 8931 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO", 8932 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 8933 "PublicDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 8934 "Counter": "2", 8935 "SampleAfterValue": "100000", 8936 "MSRIndex": "0x1A6", 8937 "MSRValue": "0x8020", 8938 "CounterMask": "0", 8939 "Invert": "0", 8940 "AnyThread": "0", 8941 "EdgeDetect": "0", 8942 "PEBS": "0", 8943 "Offcore": "1" 8944 }, 8945 { 8946 "EventCode": "0xB7", 8947 "UMask": "0x1", 8948 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE", 8949 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 8950 "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 8951 "Counter": "2", 8952 "SampleAfterValue": "100000", 8953 "MSRIndex": "0x1A6", 8954 "MSRValue": "0x120", 8955 "CounterMask": "0", 8956 "Invert": "0", 8957 "AnyThread": "0", 8958 "EdgeDetect": "0", 8959 "PEBS": "0", 8960 "Offcore": "1" 8961 }, 8962 { 8963 "EventCode": "0xB7", 8964 "UMask": "0x1", 8965 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 8966 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 8967 "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 8968 "Counter": "2", 8969 "SampleAfterValue": "100000", 8970 "MSRIndex": "0x1A6", 8971 "MSRValue": "0x220", 8972 "CounterMask": "0", 8973 "Invert": "0", 8974 "AnyThread": "0", 8975 "EdgeDetect": "0", 8976 "PEBS": "0", 8977 "Offcore": "1" 8978 }, 8979 { 8980 "EventCode": "0xB7", 8981 "UMask": "0x1", 8982 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 8983 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 8984 "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 8985 "Counter": "2", 8986 "SampleAfterValue": "100000", 8987 "MSRIndex": "0x1A6", 8988 "MSRValue": "0x420", 8989 "CounterMask": "0", 8990 "Invert": "0", 8991 "AnyThread": "0", 8992 "EdgeDetect": "0", 8993 "PEBS": "0", 8994 "Offcore": "1" 8995 }, 8996 { 8997 "EventCode": "0xB7", 8998 "UMask": "0x1", 8999 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE", 9000 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 9001 "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC", 9002 "Counter": "2", 9003 "SampleAfterValue": "100000", 9004 "MSRIndex": "0x1A6", 9005 "MSRValue": "0x720", 9006 "CounterMask": "0", 9007 "Invert": "0", 9008 "AnyThread": "0", 9009 "EdgeDetect": "0", 9010 "PEBS": "0", 9011 "Offcore": "1" 9012 }, 9013 { 9014 "EventCode": "0xB7", 9015 "UMask": "0x1", 9016 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM", 9017 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 9018 "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 9019 "Counter": "2", 9020 "SampleAfterValue": "100000", 9021 "MSRIndex": "0x1A6", 9022 "MSRValue": "0x4720", 9023 "CounterMask": "0", 9024 "Invert": "0", 9025 "AnyThread": "0", 9026 "EdgeDetect": "0", 9027 "PEBS": "0", 9028 "Offcore": "1" 9029 }, 9030 { 9031 "EventCode": "0xB7", 9032 "UMask": "0x1", 9033 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM", 9034 "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", 9035 "PublicDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", 9036 "Counter": "2", 9037 "SampleAfterValue": "100000", 9038 "MSRIndex": "0x1A6", 9039 "MSRValue": "0x4020", 9040 "CounterMask": "0", 9041 "Invert": "0", 9042 "AnyThread": "0", 9043 "EdgeDetect": "0", 9044 "PEBS": "0", 9045 "Offcore": "1" 9046 }, 9047 { 9048 "EventCode": "0xB7", 9049 "UMask": "0x1", 9050 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE", 9051 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 9052 "PublicDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 9053 "Counter": "2", 9054 "SampleAfterValue": "100000", 9055 "MSRIndex": "0x1A6", 9056 "MSRValue": "0x1820", 9057 "CounterMask": "0", 9058 "Invert": "0", 9059 "AnyThread": "0", 9060 "EdgeDetect": "0", 9061 "PEBS": "0", 9062 "Offcore": "1" 9063 }, 9064 { 9065 "EventCode": "0xB7", 9066 "UMask": "0x1", 9067 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM", 9068 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 9069 "PublicDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 9070 "Counter": "2", 9071 "SampleAfterValue": "100000", 9072 "MSRIndex": "0x1A6", 9073 "MSRValue": "0x3820", 9074 "CounterMask": "0", 9075 "Invert": "0", 9076 "AnyThread": "0", 9077 "EdgeDetect": "0", 9078 "PEBS": "0", 9079 "Offcore": "1" 9080 }, 9081 { 9082 "EventCode": "0xB7", 9083 "UMask": "0x1", 9084 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT", 9085 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 9086 "PublicDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 9087 "Counter": "2", 9088 "SampleAfterValue": "100000", 9089 "MSRIndex": "0x1A6", 9090 "MSRValue": "0x1020", 9091 "CounterMask": "0", 9092 "Invert": "0", 9093 "AnyThread": "0", 9094 "EdgeDetect": "0", 9095 "PEBS": "0", 9096 "Offcore": "1" 9097 }, 9098 { 9099 "EventCode": "0xB7", 9100 "UMask": "0x1", 9101 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM", 9102 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 9103 "PublicDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 9104 "Counter": "2", 9105 "SampleAfterValue": "100000", 9106 "MSRIndex": "0x1A6", 9107 "MSRValue": "0x820", 9108 "CounterMask": "0", 9109 "Invert": "0", 9110 "AnyThread": "0", 9111 "EdgeDetect": "0", 9112 "PEBS": "0", 9113 "Offcore": "1" 9114 }, 9115 { 9116 "EventCode": "0xB7", 9117 "UMask": "0x1", 9118 "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM", 9119 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", 9120 "PublicDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", 9121 "Counter": "2", 9122 "SampleAfterValue": "100000", 9123 "MSRIndex": "0x1A6", 9124 "MSRValue": "0x2020", 9125 "CounterMask": "0", 9126 "Invert": "0", 9127 "AnyThread": "0", 9128 "EdgeDetect": "0", 9129 "PEBS": "0", 9130 "Offcore": "1" 9131 }, 9132 { 9133 "EventCode": "0xB7", 9134 "UMask": "0x1", 9135 "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM", 9136 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 9137 "PublicDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 9138 "Counter": "2", 9139 "SampleAfterValue": "100000", 9140 "MSRIndex": "0x1A6", 9141 "MSRValue": "0x7F70", 9142 "CounterMask": "0", 9143 "Invert": "0", 9144 "AnyThread": "0", 9145 "EdgeDetect": "0", 9146 "PEBS": "0", 9147 "Offcore": "1" 9148 }, 9149 { 9150 "EventCode": "0xB7", 9151 "UMask": "0x1", 9152 "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM", 9153 "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", 9154 "PublicDescription": "Offcore prefetch requests satisfied by any DRAM", 9155 "Counter": "2", 9156 "SampleAfterValue": "100000", 9157 "MSRIndex": "0x1A6", 9158 "MSRValue": "0x6070", 9159 "CounterMask": "0", 9160 "Invert": "0", 9161 "AnyThread": "0", 9162 "EdgeDetect": "0", 9163 "PEBS": "0", 9164 "Offcore": "1" 9165 }, 9166 { 9167 "EventCode": "0xB7", 9168 "UMask": "0x1", 9169 "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS", 9170 "BriefDescription": "Offcore prefetch requests that missed the LLC", 9171 "PublicDescription": "Offcore prefetch requests that missed the LLC", 9172 "Counter": "2", 9173 "SampleAfterValue": "100000", 9174 "MSRIndex": "0x1A6", 9175 "MSRValue": "0xF870", 9176 "CounterMask": "0", 9177 "Invert": "0", 9178 "AnyThread": "0", 9179 "EdgeDetect": "0", 9180 "PEBS": "0", 9181 "Offcore": "1" 9182 }, 9183 { 9184 "EventCode": "0xB7", 9185 "UMask": "0x1", 9186 "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION", 9187 "BriefDescription": "All offcore prefetch requests", 9188 "PublicDescription": "All offcore prefetch requests", 9189 "Counter": "2", 9190 "SampleAfterValue": "100000", 9191 "MSRIndex": "0x1A6", 9192 "MSRValue": "0xFF70", 9193 "CounterMask": "0", 9194 "Invert": "0", 9195 "AnyThread": "0", 9196 "EdgeDetect": "0", 9197 "PEBS": "0", 9198 "Offcore": "1" 9199 }, 9200 { 9201 "EventCode": "0xB7", 9202 "UMask": "0x1", 9203 "EventName": "OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO", 9204 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 9205 "PublicDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 9206 "Counter": "2", 9207 "SampleAfterValue": "100000", 9208 "MSRIndex": "0x1A6", 9209 "MSRValue": "0x8070", 9210 "CounterMask": "0", 9211 "Invert": "0", 9212 "AnyThread": "0", 9213 "EdgeDetect": "0", 9214 "PEBS": "0", 9215 "Offcore": "1" 9216 }, 9217 { 9218 "EventCode": "0xB7", 9219 "UMask": "0x1", 9220 "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE", 9221 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 9222 "PublicDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 9223 "Counter": "2", 9224 "SampleAfterValue": "100000", 9225 "MSRIndex": "0x1A6", 9226 "MSRValue": "0x170", 9227 "CounterMask": "0", 9228 "Invert": "0", 9229 "AnyThread": "0", 9230 "EdgeDetect": "0", 9231 "PEBS": "0", 9232 "Offcore": "1" 9233 }, 9234 { 9235 "EventCode": "0xB7", 9236 "UMask": "0x1", 9237 "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 9238 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 9239 "PublicDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 9240 "Counter": "2", 9241 "SampleAfterValue": "100000", 9242 "MSRIndex": "0x1A6", 9243 "MSRValue": "0x270", 9244 "CounterMask": "0", 9245 "Invert": "0", 9246 "AnyThread": "0", 9247 "EdgeDetect": "0", 9248 "PEBS": "0", 9249 "Offcore": "1" 9250 }, 9251 { 9252 "EventCode": "0xB7", 9253 "UMask": "0x1", 9254 "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 9255 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 9256 "PublicDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 9257 "Counter": "2", 9258 "SampleAfterValue": "100000", 9259 "MSRIndex": "0x1A6", 9260 "MSRValue": "0x470", 9261 "CounterMask": "0", 9262 "Invert": "0", 9263 "AnyThread": "0", 9264 "EdgeDetect": "0", 9265 "PEBS": "0", 9266 "Offcore": "1" 9267 }, 9268 { 9269 "EventCode": "0xB7", 9270 "UMask": "0x1", 9271 "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE", 9272 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 9273 "PublicDescription": "Offcore prefetch requests satisfied by the LLC", 9274 "Counter": "2", 9275 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