Searched hist:fef2998203e17e4298843afb2056fbed44611734 (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/net/ethernet/altera/ |
| H A D | Kconfig | diff fef2998203e17e4298843afb2056fbed44611734 Fri Sep 02 10:32:04 CEST 2022 Maxime Chevallier <maxime.chevallier@bootlin.com> net: altera: tse: convert to phylink
Convert the Altera Triple Speed Ethernet Controller to phylink.
This controller supports MII, GMII and RGMII with its MAC, and
SGMII + 1000BaseX through a small embedded PCS.
The PCS itself has a register set very similar to what is found in a
typical 802.3 ethernet PHY, but this register set memory-mapped instead
of lying on an mdio bus.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| H A D | altera_tse_ethtool.c | diff fef2998203e17e4298843afb2056fbed44611734 Fri Sep 02 10:32:04 CEST 2022 Maxime Chevallier <maxime.chevallier@bootlin.com> net: altera: tse: convert to phylink
Convert the Altera Triple Speed Ethernet Controller to phylink.
This controller supports MII, GMII and RGMII with its MAC, and
SGMII + 1000BaseX through a small embedded PCS.
The PCS itself has a register set very similar to what is found in a
typical 802.3 ethernet PHY, but this register set memory-mapped instead
of lying on an mdio bus.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | altera_tse.h | diff fef2998203e17e4298843afb2056fbed44611734 Fri Sep 02 10:32:04 CEST 2022 Maxime Chevallier <maxime.chevallier@bootlin.com> net: altera: tse: convert to phylink
Convert the Altera Triple Speed Ethernet Controller to phylink.
This controller supports MII, GMII and RGMII with its MAC, and
SGMII + 1000BaseX through a small embedded PCS.
The PCS itself has a register set very similar to what is found in a
typical 802.3 ethernet PHY, but this register set memory-mapped instead
of lying on an mdio bus.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | altera_tse_main.c | diff fef2998203e17e4298843afb2056fbed44611734 Fri Sep 02 10:32:04 CEST 2022 Maxime Chevallier <maxime.chevallier@bootlin.com> net: altera: tse: convert to phylink
Convert the Altera Triple Speed Ethernet Controller to phylink.
This controller supports MII, GMII and RGMII with its MAC, and
SGMII + 1000BaseX through a small embedded PCS.
The PCS itself has a register set very similar to what is found in a
typical 802.3 ethernet PHY, but this register set memory-mapped instead
of lying on an mdio bus.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|