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H A Dcs42l42.hdiff fdbd256175a1e11c1ba827112d56b9a3952e1219 Fri Oct 15 15:36:16 CEST 2021 Richard Fitzgerald <rf@opensource.cirrus.com> ASoC: cs42l42: Set correct SRC MCLK

According to the datasheet the SRC MCLK must be as near as possible to
(125 * sample rate). This means it should be ~6MHz for rates up to 48k
and ~12MHz for rates above that. As per datasheet table 4-21.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20211015133619.4698-14-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
H A Dcs42l42.cdiff fdbd256175a1e11c1ba827112d56b9a3952e1219 Fri Oct 15 15:36:16 CEST 2021 Richard Fitzgerald <rf@opensource.cirrus.com> ASoC: cs42l42: Set correct SRC MCLK

According to the datasheet the SRC MCLK must be as near as possible to
(125 * sample rate). This means it should be ~6MHz for rates up to 48k
and ~12MHz for rates above that. As per datasheet table 4-21.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20211015133619.4698-14-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>