Searched hist:ef4144b1b47dba61ebf19b9567013afdba5225dd (Results 1 – 2 of 2) sorted by relevance
| /linux/Documentation/arch/arm64/ |
| H A D | silicon-errata.rst | diff ef4144b1b47dba61ebf19b9567013afdba5225dd Thu Dec 12 16:13:58 CET 2024 Bibek Kumar Patro <quic_bibekkum@quicinc.com> iommu/arm-smmu: Re-enable context caching in smmu reset operation
Default MMU-500 reset operation disables context caching in prefetch
buffer. It is however expected for context banks using the ACTLR
register to retain their prefetch value during reset and runtime
suspend.
Add config 'ARM_SMMU_MMU_500_CPRE_ERRATA' to gate this errata workaround
in default MMU-500 reset operation which defaults to 'Y' and provide
option to disable workaround for context caching in prefetch buffer as
and when needed.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Link: https://lore.kernel.org/r/20241212151402.159102-2-quic_bibekkum@quicinc.com
Signed-off-by: Will Deacon <will@kernel.org>
|
| /linux/drivers/iommu/ |
| H A D | Kconfig | diff ef4144b1b47dba61ebf19b9567013afdba5225dd Thu Dec 12 16:13:58 CET 2024 Bibek Kumar Patro <quic_bibekkum@quicinc.com> iommu/arm-smmu: Re-enable context caching in smmu reset operation
Default MMU-500 reset operation disables context caching in prefetch
buffer. It is however expected for context banks using the ACTLR
register to retain their prefetch value during reset and runtime
suspend.
Add config 'ARM_SMMU_MMU_500_CPRE_ERRATA' to gate this errata workaround
in default MMU-500 reset operation which defaults to 'Y' and provide
option to disable workaround for context caching in prefetch buffer as
and when needed.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Link: https://lore.kernel.org/r/20241212151402.159102-2-quic_bibekkum@quicinc.com
Signed-off-by: Will Deacon <will@kernel.org>
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