Searched hist:edcefb96fb07f6742fd47ac60915e76c1b77768e (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/clk/samsung/ |
| H A D | clk-exynos5-subcmu.c | diff edcefb96fb07f6742fd47ac60915e76c1b77768e Tue Mar 06 15:33:10 CET 2018 Marek Szyprowski <m.szyprowski@samsung.com> clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU
Clocks related to DISP1 block require special handling for power domain
turn on/off sequences. Till now this was handled by Exynos power domain
driver, but that approach was limited only to some special cases. This
patch moves handling of those operations to clock controller driver.
This gives more flexibility and allows fine tune values of some
clock-specific registers. This patch moves handling of those mentioned
clocks to Exynos5 sub-CMU driver instantiated from Exynos5250 driver.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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| H A D | Makefile | diff edcefb96fb07f6742fd47ac60915e76c1b77768e Tue Mar 06 15:33:10 CET 2018 Marek Szyprowski <m.szyprowski@samsung.com> clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU
Clocks related to DISP1 block require special handling for power domain
turn on/off sequences. Till now this was handled by Exynos power domain
driver, but that approach was limited only to some special cases. This
patch moves handling of those operations to clock controller driver.
This gives more flexibility and allows fine tune values of some
clock-specific registers. This patch moves handling of those mentioned
clocks to Exynos5 sub-CMU driver instantiated from Exynos5250 driver.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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| H A D | clk-exynos5250.c | diff edcefb96fb07f6742fd47ac60915e76c1b77768e Tue Mar 06 15:33:10 CET 2018 Marek Szyprowski <m.szyprowski@samsung.com> clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU
Clocks related to DISP1 block require special handling for power domain
turn on/off sequences. Till now this was handled by Exynos power domain
driver, but that approach was limited only to some special cases. This
patch moves handling of those operations to clock controller driver.
This gives more flexibility and allows fine tune values of some
clock-specific registers. This patch moves handling of those mentioned
clocks to Exynos5 sub-CMU driver instantiated from Exynos5250 driver.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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