Searched hist:eaa9d886528730bcd7213f0b22c8dd468460f495 (Results 1 – 2 of 2) sorted by relevance
| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie-common.yaml | diff eaa9d886528730bcd7213f0b22c8dd468460f495 Sun Nov 13 20:12:47 CET 2022 Serge Semin <Sergey.Semin@baikalelectronics.ru> dt-bindings: PCI: dwc: Add max-link-speed common property
In accordance with [1] DW PCIe controllers support up to Gen5 link speed.
Let's add the max-link-speed property upper bound to 5 then. The DT
bindings of the particular devices are expected to setup more strict
constraint on that parameter.
[1] Synopsys DesignWare Cores PCI Express Controller Databook, Version
5.40a, March 2019, p. 27
Link: https://lore.kernel.org/r/20221113191301.5526-7-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
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| H A D | snps,dw-pcie-ep.yaml | diff eaa9d886528730bcd7213f0b22c8dd468460f495 Sun Nov 13 20:12:47 CET 2022 Serge Semin <Sergey.Semin@baikalelectronics.ru> dt-bindings: PCI: dwc: Add max-link-speed common property
In accordance with [1] DW PCIe controllers support up to Gen5 link speed.
Let's add the max-link-speed property upper bound to 5 then. The DT
bindings of the particular devices are expected to setup more strict
constraint on that parameter.
[1] Synopsys DesignWare Cores PCI Express Controller Databook, Version
5.40a, March 2019, p. 27
Link: https://lore.kernel.org/r/20221113191301.5526-7-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
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