Searched hist:cf52db456fd02dc7a145a4f181c8490a1dfa26d9 (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/clk/meson/ |
| H A D | axg-audio.h | diff cf52db456fd02dc7a145a4f181c8490a1dfa26d9 Wed Oct 02 11:15:28 CEST 2019 Jerome Brunet <jbrunet@baylibre.com> clk: meson: axg-audio: provide clk top signal name
The peripheral clock on the sm1 goes through some muxes
and dividers before reaching the audio gates. To model that,
without repeating our self too much, the "top" clock signal
is introduced and will serve as a the parent of the gates.
On the axg and g12a, the top clock is just a pass-through to
the audio peripheral clock provided by the main controller.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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| H A D | axg-audio.c | diff cf52db456fd02dc7a145a4f181c8490a1dfa26d9 Wed Oct 02 11:15:28 CEST 2019 Jerome Brunet <jbrunet@baylibre.com> clk: meson: axg-audio: provide clk top signal name
The peripheral clock on the sm1 goes through some muxes
and dividers before reaching the audio gates. To model that,
without repeating our self too much, the "top" clock signal
is introduced and will serve as a the parent of the gates.
On the axg and g12a, the top clock is just a pass-through to
the audio peripheral clock provided by the main controller.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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