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| H A D | canyonlands.dts | diff cd85400a022335a92fa3c25827179a7ad5e02225 Fri Dec 05 02:58:49 CET 2008 Stefan Roese <sr@denx.de> powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file
With this patch the L2 cache is enabled on Canyonlands to increase the
overall performance. There is a known cache coherency issue with the L2
cache, but this is related to the high bandwidth (HB) PLB segment where
the memory address is 0x8.xxxx.xxxx (low bandwidth PLB segment is mapped
to 0x0.xxxx.xxxx). Since this HB address is currently unused it is safe
to enable the L2 cache.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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