Searched hist:c9c4ddb20c427b19c6a2a1787bf82c7b2aac25c3 (Results 1 – 2 of 2) sorted by relevance
| /linux/include/soc/tegra/ |
| H A D | pmc.h | diff c9c4ddb20c427b19c6a2a1787bf82c7b2aac25c3 Fri Sep 30 18:02:13 CEST 2022 Petlozu Pravareshwar <petlozup@nvidia.com> soc/tegra: pmc: Add I/O pad table for Tegra234
Add I/O pad table for Tegra234 to allow configuring DPD mode and
switching the pins to 1.8V or 3.3V as needed.
On Tegra234, DPD registers are reorganized such that there is a DPD_REQ
register and a DPD_STATUS register per pad group. Update the PMC driver
accordingly.
While at it, use the generated tables from tegra-pinmux-scripts to make
the formatting of these tables more consistent.
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
[treding@nvidia.com: generate tables from tegra-pinmux-scripts]
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| /linux/drivers/soc/tegra/ |
| H A D | pmc.c | diff c9c4ddb20c427b19c6a2a1787bf82c7b2aac25c3 Fri Sep 30 18:02:13 CEST 2022 Petlozu Pravareshwar <petlozup@nvidia.com> soc/tegra: pmc: Add I/O pad table for Tegra234
Add I/O pad table for Tegra234 to allow configuring DPD mode and
switching the pins to 1.8V or 3.3V as needed.
On Tegra234, DPD registers are reorganized such that there is a DPD_REQ
register and a DPD_STATUS register per pad group. Update the PMC driver
accordingly.
While at it, use the generated tables from tegra-pinmux-scripts to make
the formatting of these tables more consistent.
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
[treding@nvidia.com: generate tables from tegra-pinmux-scripts]
Signed-off-by: Thierry Reding <treding@nvidia.com>
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