Searched hist:c46c5fb725bedd73cf33511b6a52d82b57eaba2a (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_gt_regs.h | diff c46c5fb725bedd73cf33511b6a52d82b57eaba2a Thu Dec 01 23:22:10 CET 2022 Matt Roper <matthew.d.roper@intel.com> drm/i915/gen12: Apply recommended L3 hashing mask
The TGL/RKL/DG1/ADL performance tuning guide suggests programming a
literal value of 0x2FC0100F for this register. The register's hardware
default value is 0x2FC0108F, so this translates to just clearing one
bit.
Take this opportunity to also clean up the register definition and
re-write its existing bits/fields in the preferred notation.
Bspec: 31870
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221201222210.344152-1-matthew.d.roper@intel.com
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| H A D | intel_workarounds.c | diff c46c5fb725bedd73cf33511b6a52d82b57eaba2a Thu Dec 01 23:22:10 CET 2022 Matt Roper <matthew.d.roper@intel.com> drm/i915/gen12: Apply recommended L3 hashing mask
The TGL/RKL/DG1/ADL performance tuning guide suggests programming a
literal value of 0x2FC0100F for this register. The register's hardware
default value is 0x2FC0108F, so this translates to just clearing one
bit.
Take this opportunity to also clean up the register definition and
re-write its existing bits/fields in the preferred notation.
Bspec: 31870
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221201222210.344152-1-matthew.d.roper@intel.com
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