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| /linux/drivers/clk/zynqmp/ |
| H A D | divider.c | diff c06e64407e031e71c67f45f07981510ca4c880a1 Tue Mar 19 11:01:46 CET 2019 Michael Tretter <m.tretter@pengutronix.de> clk: zynqmp: fix check for fractional clock
The firmware sets BIT(13) in clkflag to mark a divider as fractional
divider. The clock driver copies the clkflag straight to the flags of
the common clock framework. In the common clk framework flags, BIT(13)
is defined as CLK_DUTY_CYCLE_PARENT.
Add a new field to the zynqmp_clk_divider to specify if a divider is a
fractional devider. Set this field based on the clkflag when registering
a divider.
At the same time, unset BIT(13) from clkflag when copying the flags to
the common clk framework flags.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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