Searched hist:bb1fcc70d98f040e3cc469b079d3f38fc541cb95 (Results 1 – 4 of 4) sorted by relevance
| /linux/arch/x86/kvm/mmu/ |
| H A D | paging_tmpl.h | diff bb1fcc70d98f040e3cc469b079d3f38fc541cb95 Tue Mar 03 03:02:36 CET 2020 Sean Christopherson <sean.j.christopherson@intel.com> KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT
Add support for 5-level nested EPT, and advertise said support in the
EPT capabilities MSR. KVM's MMU can already handle 5-level legacy page
tables, there's no reason to force an L1 VMM to use shadow paging if it
wants to employ 5-level page tables.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
| /linux/arch/x86/include/asm/ |
| H A D | vmx.h | diff bb1fcc70d98f040e3cc469b079d3f38fc541cb95 Tue Mar 03 03:02:36 CET 2020 Sean Christopherson <sean.j.christopherson@intel.com> KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT
Add support for 5-level nested EPT, and advertise said support in the
EPT capabilities MSR. KVM's MMU can already handle 5-level legacy page
tables, there's no reason to force an L1 VMM to use shadow paging if it
wants to employ 5-level page tables.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
| /linux/arch/x86/kvm/vmx/ |
| H A D | nested.c | diff bb1fcc70d98f040e3cc469b079d3f38fc541cb95 Tue Mar 03 03:02:36 CET 2020 Sean Christopherson <sean.j.christopherson@intel.com> KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT
Add support for 5-level nested EPT, and advertise said support in the
EPT capabilities MSR. KVM's MMU can already handle 5-level legacy page
tables, there's no reason to force an L1 VMM to use shadow paging if it
wants to employ 5-level page tables.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
| H A D | vmx.c | diff bb1fcc70d98f040e3cc469b079d3f38fc541cb95 Tue Mar 03 03:02:36 CET 2020 Sean Christopherson <sean.j.christopherson@intel.com> KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT
Add support for 5-level nested EPT, and advertise said support in the
EPT capabilities MSR. KVM's MMU can already handle 5-level legacy page
tables, there's no reason to force an L1 VMM to use shadow paging if it
wants to employ 5-level page tables.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|