Searched hist:bae833414bfe6a33f6d55d5e0eb38e5989c6fe7b (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/mips/boot/dts/ralink/ |
| H A D | mt7621-gnubee-gb-pc1.dts | diff bae833414bfe6a33f6d55d5e0eb38e5989c6fe7b Sat Feb 11 11:49:15 CET 2023 Arınç ÜNAL <arinc.unal@arinc9.com> mips: dts: ralink: mt7621: add port@5 as CPU port
On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is
connected to the second MAC of the SoC as a CPU port. Add the port and set
up the second MAC on the bindings. Revert PHY muxing on GB-PC1.
There's an external PHY connected to the second MAC of the SoC on GB-PC2,
therefore, disable port@5 for this device.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| H A D | mt7621-gnubee-gb-pc2.dts | diff bae833414bfe6a33f6d55d5e0eb38e5989c6fe7b Sat Feb 11 11:49:15 CET 2023 Arınç ÜNAL <arinc.unal@arinc9.com> mips: dts: ralink: mt7621: add port@5 as CPU port
On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is
connected to the second MAC of the SoC as a CPU port. Add the port and set
up the second MAC on the bindings. Revert PHY muxing on GB-PC1.
There's an external PHY connected to the second MAC of the SoC on GB-PC2,
therefore, disable port@5 for this device.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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