Searched hist:ba8b0ee81fbbc249e60f84bf097bd56e8047c742 (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/phy/hisilicon/ |
| H A D | Makefile | diff ba8b0ee81fbbc249e60f84bf097bd56e8047c742 Fri Mar 09 15:47:01 CET 2018 Pengcheng Li <lpc.li@hisilicon.com> phy: add inno-usb2-phy driver for hi3798cv200 SoC
It adds inno-usb2-phy driver for hi3798cv200 SoC USB 2.0 support. One
inno-usb2-phy device can support up to two PHY ports. While there is
device level reference clock and power reset to be controlled, each PHY
port has its own utmi reset that needs to assert/de-assert as needed.
Hi3798cv200 needs to access PHY port0 register via particular peripheral
syscon controller register to control PHY, like turning on PHY clock.
Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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| H A D | phy-hisi-inno-usb2.c | ba8b0ee81fbbc249e60f84bf097bd56e8047c742 Fri Mar 09 15:47:01 CET 2018 Pengcheng Li <lpc.li@hisilicon.com> phy: add inno-usb2-phy driver for hi3798cv200 SoC
It adds inno-usb2-phy driver for hi3798cv200 SoC USB 2.0 support. One
inno-usb2-phy device can support up to two PHY ports. While there is
device level reference clock and power reset to be controlled, each PHY
port has its own utmi reset that needs to assert/de-assert as needed.
Hi3798cv200 needs to access PHY port0 register via particular peripheral
syscon controller register to control PHY, like turning on PHY clock.
Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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| H A D | Kconfig | diff ba8b0ee81fbbc249e60f84bf097bd56e8047c742 Fri Mar 09 15:47:01 CET 2018 Pengcheng Li <lpc.li@hisilicon.com> phy: add inno-usb2-phy driver for hi3798cv200 SoC
It adds inno-usb2-phy driver for hi3798cv200 SoC USB 2.0 support. One
inno-usb2-phy device can support up to two PHY ports. While there is
device level reference clock and power reset to be controlled, each PHY
port has its own utmi reset that needs to assert/de-assert as needed.
Hi3798cv200 needs to access PHY port0 register via particular peripheral
syscon controller register to control PHY, like turning on PHY clock.
Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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