Searched hist:b977d81946d4e7f7c61c6c73ca5cb736b5f7f66c (Results 1 – 5 of 5) sorted by relevance
| /freebsd/sys/riscv/include/ |
| H A D | pte.h | diff b977d81946d4e7f7c61c6c73ca5cb736b5f7f66c Thu Oct 18 17:25:07 CEST 2018 Ruslan Bukin <br@FreeBSD.org> Support RISC-V implementations that do not manage the A and D bits
(e.g. RocketChip, lowRISC and derivatives).
RISC-V page table entries support A (accessed) and D (dirty) bits. The
spec makes hardware support for these bits optional. Implementations that
do not manage these bits in hardware raise page faults for accesses to a
valid page without A set and writes to a writable page without D set.
Check for these types of faults when handling a page fault and fixup the
PTE without calling vm_fault if they occur.
Reviewed by: jhb, markj
Approved by: re (gjb)
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D17424
|
| H A D | pmap.h | diff b977d81946d4e7f7c61c6c73ca5cb736b5f7f66c Thu Oct 18 17:25:07 CEST 2018 Ruslan Bukin <br@FreeBSD.org> Support RISC-V implementations that do not manage the A and D bits
(e.g. RocketChip, lowRISC and derivatives).
RISC-V page table entries support A (accessed) and D (dirty) bits. The
spec makes hardware support for these bits optional. Implementations that
do not manage these bits in hardware raise page faults for accesses to a
valid page without A set and writes to a writable page without D set.
Check for these types of faults when handling a page fault and fixup the
PTE without calling vm_fault if they occur.
Reviewed by: jhb, markj
Approved by: re (gjb)
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D17424
|
| /freebsd/sys/riscv/riscv/ |
| H A D | locore.S | diff b977d81946d4e7f7c61c6c73ca5cb736b5f7f66c Thu Oct 18 17:25:07 CEST 2018 Ruslan Bukin <br@FreeBSD.org> Support RISC-V implementations that do not manage the A and D bits
(e.g. RocketChip, lowRISC and derivatives).
RISC-V page table entries support A (accessed) and D (dirty) bits. The
spec makes hardware support for these bits optional. Implementations that
do not manage these bits in hardware raise page faults for accesses to a
valid page without A set and writes to a writable page without D set.
Check for these types of faults when handling a page fault and fixup the
PTE without calling vm_fault if they occur.
Reviewed by: jhb, markj
Approved by: re (gjb)
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D17424
|
| H A D | trap.c | diff b977d81946d4e7f7c61c6c73ca5cb736b5f7f66c Thu Oct 18 17:25:07 CEST 2018 Ruslan Bukin <br@FreeBSD.org> Support RISC-V implementations that do not manage the A and D bits
(e.g. RocketChip, lowRISC and derivatives).
RISC-V page table entries support A (accessed) and D (dirty) bits. The
spec makes hardware support for these bits optional. Implementations that
do not manage these bits in hardware raise page faults for accesses to a
valid page without A set and writes to a writable page without D set.
Check for these types of faults when handling a page fault and fixup the
PTE without calling vm_fault if they occur.
Reviewed by: jhb, markj
Approved by: re (gjb)
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D17424
|
| H A D | pmap.c | diff b977d81946d4e7f7c61c6c73ca5cb736b5f7f66c Thu Oct 18 17:25:07 CEST 2018 Ruslan Bukin <br@FreeBSD.org> Support RISC-V implementations that do not manage the A and D bits
(e.g. RocketChip, lowRISC and derivatives).
RISC-V page table entries support A (accessed) and D (dirty) bits. The
spec makes hardware support for these bits optional. Implementations that
do not manage these bits in hardware raise page faults for accesses to a
valid page without A set and writes to a writable page without D set.
Check for these types of faults when handling a page fault and fixup the
PTE without calling vm_fault if they occur.
Reviewed by: jhb, markj
Approved by: re (gjb)
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D17424
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