Searched hist:b795fadfc46bc497257435d4d9e57f487f521fd1 (Results 1 – 4 of 4) sorted by relevance
| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | ac5-98dx35xx.dtsi | b795fadfc46bc497257435d4d9e57f487f521fd1 Tue Jul 05 21:09:20 CEST 2022 Chris Packham <chris.packham@alliedtelesis.co.nz> arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
The 98DX2530 SoC is the Control and Management CPU integrated into
the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
referred to as AlleyCat5 and AlleyCat5X).
These files have been taken from the Marvell SDK and lightly cleaned
up with the License and copyright retained.
gregory.clement: use specific cpu type: cortex-a55 instead of armv8 in
cpu nodes, armv8 being reserved for the arm virtual models that are
not meant to implement a particular CPU type.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
| H A D | ac5-98dx35xx-rd.dts | b795fadfc46bc497257435d4d9e57f487f521fd1 Tue Jul 05 21:09:20 CEST 2022 Chris Packham <chris.packham@alliedtelesis.co.nz> arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
The 98DX2530 SoC is the Control and Management CPU integrated into
the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
referred to as AlleyCat5 and AlleyCat5X).
These files have been taken from the Marvell SDK and lightly cleaned
up with the License and copyright retained.
gregory.clement: use specific cpu type: cortex-a55 instead of armv8 in
cpu nodes, armv8 being reserved for the arm virtual models that are
not meant to implement a particular CPU type.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
| H A D | ac5-98dx25xx.dtsi | b795fadfc46bc497257435d4d9e57f487f521fd1 Tue Jul 05 21:09:20 CEST 2022 Chris Packham <chris.packham@alliedtelesis.co.nz> arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
The 98DX2530 SoC is the Control and Management CPU integrated into
the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
referred to as AlleyCat5 and AlleyCat5X).
These files have been taken from the Marvell SDK and lightly cleaned
up with the License and copyright retained.
gregory.clement: use specific cpu type: cortex-a55 instead of armv8 in
cpu nodes, armv8 being reserved for the arm virtual models that are
not meant to implement a particular CPU type.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
| H A D | Makefile | diff b795fadfc46bc497257435d4d9e57f487f521fd1 Tue Jul 05 21:09:20 CEST 2022 Chris Packham <chris.packham@alliedtelesis.co.nz> arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
The 98DX2530 SoC is the Control and Management CPU integrated into
the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
referred to as AlleyCat5 and AlleyCat5X).
These files have been taken from the Marvell SDK and lightly cleaned
up with the License and copyright retained.
gregory.clement: use specific cpu type: cortex-a55 instead of armv8 in
cpu nodes, armv8 being reserved for the arm virtual models that are
not meant to implement a particular CPU type.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|