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/linux/include/dt-bindings/clock/
H A Dtegra124-car-common.hdiff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux

PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.

So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
/linux/drivers/clk/tegra/
H A Dclk-id.hdiff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux

PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.

So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
H A Dclk-tegra-periph.cdiff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux

PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.

So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
H A Dclk-tegra124.cdiff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux

PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.

So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
H A Dclk-tegra114.cdiff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux

PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.

So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>