Searched hist:b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 (Results 1 – 5 of 5) sorted by relevance
/linux/include/dt-bindings/clock/ |
H A D | tegra124-car-common.h | diff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock.
So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
|
/linux/drivers/clk/tegra/ |
H A D | clk-id.h | diff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock.
So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
|
H A D | clk-tegra-periph.c | diff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock.
So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
|
H A D | clk-tegra124.c | diff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock.
So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
|
H A D | clk-tegra114.c | diff b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Tue Dec 09 07:59:59 CET 2014 Mark Zhang <markz@nvidia.com> clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock.
So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
|