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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra124-dfll-fcpu.c | diff b0dcfb78dc6aec8698ab5900dfdf6aeae0830815 Fri Jan 04 04:06:47 CET 2019 Peter De Schrijver <pdeschrijver@nvidia.com> clk: tegra: dfll: registration for multiple SoCs
In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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