Searched hist:adc4cefae9cfafc1c88b789021266d6f09a0ecef (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/microblaze/include/asm/ |
| H A D | xilinx_mb_manager.h | diff adc4cefae9cfafc1c88b789021266d6f09a0ecef Mon Jun 27 08:40:24 CEST 2022 Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> microblaze: Add support for error injection
To inject the error using the tmr inject IP reset vectors need to be placed
in lmb(bram) due to the limitation in HW when this code runs out of DDR.
Below code adds the error inject code to the .init.ivt section to copy
it in machine_early_init to lmb/Bram location. C_BASE_VECTORS which allow
moving reset vectors out of 0 location is not currently supported by
Microblaze architecture, that's why all the time reset vectors with
injection code is all the time copied to address 0.
As of now getting this functionality working CPU switches to real mode
and simply jumps to bram, which causes triggering of fault which continues
to call_xmb_manager_break break handler which will at the end calls the
error count callback function and performs recovery.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Link: https://lore.kernel.org/r/20220627064024.771037-4-appana.durga.rao@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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| /linux/arch/microblaze/kernel/ |
| H A D | entry.S | diff adc4cefae9cfafc1c88b789021266d6f09a0ecef Mon Jun 27 08:40:24 CEST 2022 Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> microblaze: Add support for error injection
To inject the error using the tmr inject IP reset vectors need to be placed
in lmb(bram) due to the limitation in HW when this code runs out of DDR.
Below code adds the error inject code to the .init.ivt section to copy
it in machine_early_init to lmb/Bram location. C_BASE_VECTORS which allow
moving reset vectors out of 0 location is not currently supported by
Microblaze architecture, that's why all the time reset vectors with
injection code is all the time copied to address 0.
As of now getting this functionality working CPU switches to real mode
and simply jumps to bram, which causes triggering of fault which continues
to call_xmb_manager_break break handler which will at the end calls the
error count callback function and performs recovery.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Link: https://lore.kernel.org/r/20220627064024.771037-4-appana.durga.rao@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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