Searched hist:a91bb605ec5f93676e503267c89469d02c5b4cbc (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/clk/tegra/ |
| H A D | clk-id.h | diff a91bb605ec5f93676e503267c89469d02c5b4cbc Mon Apr 20 15:13:36 CEST 2015 Thierry Reding <treding@nvidia.com> clk: tegra: Add sor_safe clock
The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| H A D | clk-tegra210.c | diff a91bb605ec5f93676e503267c89469d02c5b4cbc Mon Apr 20 15:13:36 CEST 2015 Thierry Reding <treding@nvidia.com> clk: tegra: Add sor_safe clock
The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|