Searched hist:a6581ebe76856bf23d1a7f3ee95828173b560a05 (Results 1 – 7 of 7) sorted by relevance
| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_memirq_types.h | a6581ebe76856bf23d1a7f3ee95828173b560a05 Mon Dec 18 17:53:41 CET 2023 Michal Wajdeczko <michal.wajdeczko@intel.com> drm/xe/vf: Introduce Memory Based Interrupts Handler
The register based interrupts infrastructure does not scale
efficiently to allow delivering interrupts to a large number
of virtual machines. Memory based interrupt reporting provides
an efficient and scalable infrastructure.
Define handler to read and dispatch memory based interrupts.
We will use this handler in upcoming patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-8-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
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| H A D | xe_memirq.h | a6581ebe76856bf23d1a7f3ee95828173b560a05 Mon Dec 18 17:53:41 CET 2023 Michal Wajdeczko <michal.wajdeczko@intel.com> drm/xe/vf: Introduce Memory Based Interrupts Handler
The register based interrupts infrastructure does not scale
efficiently to allow delivering interrupts to a large number
of virtual machines. Memory based interrupt reporting provides
an efficient and scalable infrastructure.
Define handler to read and dispatch memory based interrupts.
We will use this handler in upcoming patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-8-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
|
| H A D | xe_memirq.c | a6581ebe76856bf23d1a7f3ee95828173b560a05 Mon Dec 18 17:53:41 CET 2023 Michal Wajdeczko <michal.wajdeczko@intel.com> drm/xe/vf: Introduce Memory Based Interrupts Handler
The register based interrupts infrastructure does not scale
efficiently to allow delivering interrupts to a large number
of virtual machines. Memory based interrupt reporting provides
an efficient and scalable infrastructure.
Define handler to read and dispatch memory based interrupts.
We will use this handler in upcoming patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-8-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
|
| H A D | xe_device.h | diff a6581ebe76856bf23d1a7f3ee95828173b560a05 Mon Dec 18 17:53:41 CET 2023 Michal Wajdeczko <michal.wajdeczko@intel.com> drm/xe/vf: Introduce Memory Based Interrupts Handler
The register based interrupts infrastructure does not scale
efficiently to allow delivering interrupts to a large number
of virtual machines. Memory based interrupt reporting provides
an efficient and scalable infrastructure.
Define handler to read and dispatch memory based interrupts.
We will use this handler in upcoming patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-8-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
|
| H A D | Makefile | diff a6581ebe76856bf23d1a7f3ee95828173b560a05 Mon Dec 18 17:53:41 CET 2023 Michal Wajdeczko <michal.wajdeczko@intel.com> drm/xe/vf: Introduce Memory Based Interrupts Handler
The register based interrupts infrastructure does not scale
efficiently to allow delivering interrupts to a large number
of virtual machines. Memory based interrupt reporting provides
an efficient and scalable infrastructure.
Define handler to read and dispatch memory based interrupts.
We will use this handler in upcoming patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-8-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
|
| H A D | xe_device_types.h | diff a6581ebe76856bf23d1a7f3ee95828173b560a05 Mon Dec 18 17:53:41 CET 2023 Michal Wajdeczko <michal.wajdeczko@intel.com> drm/xe/vf: Introduce Memory Based Interrupts Handler
The register based interrupts infrastructure does not scale
efficiently to allow delivering interrupts to a large number
of virtual machines. Memory based interrupt reporting provides
an efficient and scalable infrastructure.
Define handler to read and dispatch memory based interrupts.
We will use this handler in upcoming patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-8-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
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| H A D | xe_device.c | diff a6581ebe76856bf23d1a7f3ee95828173b560a05 Mon Dec 18 17:53:41 CET 2023 Michal Wajdeczko <michal.wajdeczko@intel.com> drm/xe/vf: Introduce Memory Based Interrupts Handler
The register based interrupts infrastructure does not scale
efficiently to allow delivering interrupts to a large number
of virtual machines. Memory based interrupt reporting provides
an efficient and scalable infrastructure.
Define handler to read and dispatch memory based interrupts.
We will use this handler in upcoming patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-8-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
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