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| H A D | socionext,uniphier-pcie-ep.yaml | diff a5c1bf7e9a4638fbb27461e9801f07204b50dcb6 Sun Aug 18 19:28:43 CEST 2024 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".
Add missing top-level constraints for clock-names and reset-names.
Link: https://lore.kernel.org/linux-pci/20240818172843.121787-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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