Searched hist:a4b5bd9abcf5b0586de68722ff8e9b91020279bf (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/mips/mm/ |
| H A D | cerr-sb1.c | diff a4b5bd9abcf5b0586de68722ff8e9b91020279bf Thu Oct 20 08:57:40 CEST 2005 Andrew Isaacson <adi@broadcom.com> SB1 cache exception handling.
Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and
SB1_CEX_STALL, allowing configurable behavior on cache errors.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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| H A D | cex-sb1.S | diff a4b5bd9abcf5b0586de68722ff8e9b91020279bf Thu Oct 20 08:57:40 CEST 2005 Andrew Isaacson <adi@broadcom.com> SB1 cache exception handling.
Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and
SB1_CEX_STALL, allowing configurable behavior on cache errors.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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| /linux/arch/mips/sibyte/ |
| H A D | Kconfig | diff a4b5bd9abcf5b0586de68722ff8e9b91020279bf Thu Oct 20 08:57:40 CEST 2005 Andrew Isaacson <adi@broadcom.com> SB1 cache exception handling.
Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and
SB1_CEX_STALL, allowing configurable behavior on cache errors.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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