Searched hist:a3c83ff20c64a0ea3580aa7ed2953ff1602334dd (Results 1 – 2 of 2) sorted by relevance
| /linux/include/dt-bindings/reset/ |
| H A D | tegra124-car.h | a3c83ff20c64a0ea3580aa7ed2953ff1602334dd Tue May 19 13:43:30 CEST 2015 Paul Walmsley <pwalmsley@nvidia.com> clk: tegra: Add DFLL DVCO reset control for Tegra124
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.
Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
saving hours of debugging time.
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
[ttynkkynen: ported to tegra124 from tegra114]
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
[mikko.perttunen: ported to special reset callback]
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra124.c | diff a3c83ff20c64a0ea3580aa7ed2953ff1602334dd Tue May 19 13:43:30 CEST 2015 Paul Walmsley <pwalmsley@nvidia.com> clk: tegra: Add DFLL DVCO reset control for Tegra124
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.
Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
saving hours of debugging time.
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
[ttynkkynen: ported to tegra124 from tegra114]
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
[mikko.perttunen: ported to special reset callback]
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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