Searched hist:a2112949e5f96c1b95aedfb9e2f0401e6c4f864f (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_rtp_types.h | diff a2112949e5f96c1b95aedfb9e2f0401e6c4f864f Wed Sep 06 03:20:50 CEST 2023 Lucas De Marchi <lucas.demarchi@intel.com> drm/xe/reg_sr: Simplify check for masked registers
For all RTP actions, clr_bits is a superset of the bits being modified.
That's also why the check for "changing all bits" can be done with
`clr_bits + 1`. So always use clr_bits for setting the upper bits of a
masked register.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://lore.kernel.org/r/20230906012053.1733755-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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| H A D | xe_reg_sr.c | diff a2112949e5f96c1b95aedfb9e2f0401e6c4f864f Wed Sep 06 03:20:50 CEST 2023 Lucas De Marchi <lucas.demarchi@intel.com> drm/xe/reg_sr: Simplify check for masked registers
For all RTP actions, clr_bits is a superset of the bits being modified.
That's also why the check for "changing all bits" can be done with
`clr_bits + 1`. So always use clr_bits for setting the upper bits of a
masked register.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://lore.kernel.org/r/20230906012053.1733755-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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