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/linux/drivers/memory/tegra/
H A Dtegra210-emc.hdiff 9b9d8632f51f3609dfdfe8efc3c1e4e773c6c385 Wed May 29 10:21:37 CEST 2019 Joseph Lo <josephl@nvidia.com> memory: tegra: Add EMC scaling sequence code for Tegra210

This patch includes the sequence for clock tuning and the dynamic
training mechanism for the clock above 800MHz.

And historically there have been different sequences to change the EMC
clock. The sequence to be used is specified in the EMC table.
However, for the currently supported upstreaming platform, only the most
recent sequence is used. So only support that in this patch.

Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
H A Dtegra210-emc-cc-r21021.c9b9d8632f51f3609dfdfe8efc3c1e4e773c6c385 Wed May 29 10:21:37 CEST 2019 Joseph Lo <josephl@nvidia.com> memory: tegra: Add EMC scaling sequence code for Tegra210

This patch includes the sequence for clock tuning and the dynamic
training mechanism for the clock above 800MHz.

And historically there have been different sequences to change the EMC
clock. The sequence to be used is specified in the EMC table.
However, for the currently supported upstreaming platform, only the most
recent sequence is used. So only support that in this patch.

Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
H A Dtegra210-emc-core.cdiff 9b9d8632f51f3609dfdfe8efc3c1e4e773c6c385 Wed May 29 10:21:37 CEST 2019 Joseph Lo <josephl@nvidia.com> memory: tegra: Add EMC scaling sequence code for Tegra210

This patch includes the sequence for clock tuning and the dynamic
training mechanism for the clock above 800MHz.

And historically there have been different sequences to change the EMC
clock. The sequence to be used is specified in the EMC table.
However, for the currently supported upstreaming platform, only the most
recent sequence is used. So only support that in this patch.

Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
H A DMakefilediff 9b9d8632f51f3609dfdfe8efc3c1e4e773c6c385 Wed May 29 10:21:37 CEST 2019 Joseph Lo <josephl@nvidia.com> memory: tegra: Add EMC scaling sequence code for Tegra210

This patch includes the sequence for clock tuning and the dynamic
training mechanism for the clock above 800MHz.

And historically there have been different sequences to change the EMC
clock. The sequence to be used is specified in the EMC table.
However, for the currently supported upstreaming platform, only the most
recent sequence is used. So only support that in this patch.

Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>