Searched hist:"95 fcec713259d440626526ed96ff5d3bac6179ea" (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/arm64/kernel/ |
| H A D | entry-fpsimd.S | diff 95fcec713259d440626526ed96ff5d3bac6179ea Mon Jan 16 17:04:45 CET 2023 Mark Brown <broonie@kernel.org> arm64/sme: Implement context switching for ZT0
When the system supports SME2 the ZT0 register must be context switched as
part of the floating point state. This register is stored immediately
after ZA in memory and is only accessible when PSTATE.ZA is set so we
handle it in the same functions we use to save and restore ZA.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20221208-arm64-sme2-v4-10-f2fa0aef982f@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|
| H A D | fpsimd.c | diff 95fcec713259d440626526ed96ff5d3bac6179ea Mon Jan 16 17:04:45 CET 2023 Mark Brown <broonie@kernel.org> arm64/sme: Implement context switching for ZT0
When the system supports SME2 the ZT0 register must be context switched as
part of the floating point state. This register is stored immediately
after ZA in memory and is only accessible when PSTATE.ZA is set so we
handle it in the same functions we use to save and restore ZA.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20221208-arm64-sme2-v4-10-f2fa0aef982f@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|
| /linux/arch/arm64/include/asm/ |
| H A D | fpsimd.h | diff 95fcec713259d440626526ed96ff5d3bac6179ea Mon Jan 16 17:04:45 CET 2023 Mark Brown <broonie@kernel.org> arm64/sme: Implement context switching for ZT0
When the system supports SME2 the ZT0 register must be context switched as
part of the floating point state. This register is stored immediately
after ZA in memory and is only accessible when PSTATE.ZA is set so we
handle it in the same functions we use to save and restore ZA.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20221208-arm64-sme2-v4-10-f2fa0aef982f@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|