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H A Dtraps_misaligned.c956d705dd279f70d5a222375fa97b637d6e8c43d Mon Mar 16 01:47:36 CET 2020 Damien Le Moal <damien.lemoal@wdc.com> riscv: Unaligned load/store handling for M_MODE

Add handlers for unaligned load and store traps that may be generated
by applications. Code heavily inspired from the OpenSBI project.
Handling of the unaligned access traps is suitable for applications
compiled with or without compressed instructions and is independent of
the kernel CONFIG_RISCV_ISA_C option value.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
H A Dtraps.cdiff 956d705dd279f70d5a222375fa97b637d6e8c43d Mon Mar 16 01:47:36 CET 2020 Damien Le Moal <damien.lemoal@wdc.com> riscv: Unaligned load/store handling for M_MODE

Add handlers for unaligned load and store traps that may be generated
by applications. Code heavily inspired from the OpenSBI project.
Handling of the unaligned access traps is suitable for applications
compiled with or without compressed instructions and is independent of
the kernel CONFIG_RISCV_ISA_C option value.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
H A DMakefilediff 956d705dd279f70d5a222375fa97b637d6e8c43d Mon Mar 16 01:47:36 CET 2020 Damien Le Moal <damien.lemoal@wdc.com> riscv: Unaligned load/store handling for M_MODE

Add handlers for unaligned load and store traps that may be generated
by applications. Code heavily inspired from the OpenSBI project.
Handling of the unaligned access traps is suitable for applications
compiled with or without compressed instructions and is independent of
the kernel CONFIG_RISCV_ISA_C option value.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>