Searched hist:"85848 dd7ab75fce1134856228582a8df522c91d9" (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/arm/include/asm/ |
| H A D | smp_plat.h | diff 85848dd7ab75fce1134856228582a8df522c91d9 Mon Sep 13 16:58:37 CEST 2010 Catalin Marinas <catalin.marinas@arm.com> ARM: 6381/1: Use lazy cache flushing on ARMv7 SMP systems
ARMv7 processors like Cortex-A9 broadcast the cache maintenance
operations in hardware. This patch allows the
flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
similar to the UP case.
Note that cache flushing on SMP systems now takes place via the
set_pte_at() call (__sync_icache_dcache) and there is no race with other
CPUs executing code from the new PTE before the cache flushing took
place.
Tested-by: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| /linux/arch/arm/mm/ |
| H A D | flush.c | diff 85848dd7ab75fce1134856228582a8df522c91d9 Mon Sep 13 16:58:37 CEST 2010 Catalin Marinas <catalin.marinas@arm.com> ARM: 6381/1: Use lazy cache flushing on ARMv7 SMP systems
ARMv7 processors like Cortex-A9 broadcast the cache maintenance
operations in hardware. This patch allows the
flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
similar to the UP case.
Note that cache flushing on SMP systems now takes place via the
set_pte_at() call (__sync_icache_dcache) and there is no race with other
CPUs executing code from the new PTE before the cache flushing took
place.
Tested-by: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|