Searched hist:"83508093 f448e929bf55d07dd08246d22b03d753" (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/arm/mach-sa1100/include/mach/ |
| H A D | irqs.h | diff 83508093f448e929bf55d07dd08246d22b03d753 Thu Jan 15 02:29:16 CET 2015 Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> ARM: 8278/1: sa1100: split irq handling for low GPIOs
Low GPIO pins use an interrupt in SC interrupts space. However it's
possible to handle them as if all the GPIO interrupts are instead tied
to single GPIO handler, which later decodes GEDR register and
chain-calls next IRQ handler. So split first 11 interrupts into system
part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of
system controller interrupts and real GPIO interrupts
(IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then
decodes and calls next handler.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| /linux/drivers/gpio/ |
| H A D | gpio-sa1100.c | diff 83508093f448e929bf55d07dd08246d22b03d753 Thu Jan 15 02:29:16 CET 2015 Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> ARM: 8278/1: sa1100: split irq handling for low GPIOs
Low GPIO pins use an interrupt in SC interrupts space. However it's
possible to handle them as if all the GPIO interrupts are instead tied
to single GPIO handler, which later decodes GEDR register and
chain-calls next IRQ handler. So split first 11 interrupts into system
part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of
system controller interrupts and real GPIO interrupts
(IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then
decodes and calls next handler.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|