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| /linux/drivers/phy/cadence/ |
| H A D | phy-cadence-sierra.c | diff 7a5ad9b4b98cd95f02ec12c895e80bc521fbf9ec Thu Dec 23 07:01:32 CET 2021 Swapnil Jakhade <sjakhade@cadence.com> phy: cadence: Sierra: Update single link PCIe register configuration
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-11-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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