Searched hist:"71 d5049b053876afbde6c3273250b76935494ab2" (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/x86/include/asm/ |
| H A D | realmode.h | diff 71d5049b053876afbde6c3273250b76935494ab2 Thu Dec 02 16:32:25 CET 2021 Joerg Roedel <jroedel@suse.de> x86/mm: Flush global TLB when switching to trampoline page-table
Move the switching code into a function so that it can be re-used and
add a global TLB flush. This makes sure that usage of memory which is
not mapped in the trampoline page-table is reliably caught.
Also move the clearing of CR4.PCIDE before the CR3 switch because the
cr4_clear_bits() function will access data not mapped into the
trampoline page-table.
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20211202153226.22946-4-joro@8bytes.org
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| /linux/arch/x86/realmode/ |
| H A D | init.c | diff 71d5049b053876afbde6c3273250b76935494ab2 Thu Dec 02 16:32:25 CET 2021 Joerg Roedel <jroedel@suse.de> x86/mm: Flush global TLB when switching to trampoline page-table
Move the switching code into a function so that it can be re-used and
add a global TLB flush. This makes sure that usage of memory which is
not mapped in the trampoline page-table is reliably caught.
Also move the clearing of CR4.PCIDE before the CR3 switch because the
cr4_clear_bits() function will access data not mapped into the
trampoline page-table.
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20211202153226.22946-4-joro@8bytes.org
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