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| H A D | andestech,ax45mp-cache.yaml | diff 6df241aacef5f9175b818a80c2ee018697efabc0 Tue Oct 03 12:47:59 CEST 2023 Geert Uytterhoeven <geert+renesas@glider.be> dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example
The unit address in the example does not match the reg property.
Correct the unit address to match reality.
Fixes: 3e7bf4685e42786d ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/7b93655219a6ad696dd3faa9f36fde6b094694a9.1696330005.git.geert+renesas@glider.be
Signed-off-by: Rob Herring <robh@kernel.org>
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