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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a779g0.dtsi | diff 68c9c53d45fa9c48a89d8a9a4d1555b9e91add69 Mon Nov 14 13:49:01 CET 2022 Geert Uytterhoeven <geert+renesas@glider.be> arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores
Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4H (R8A779G0) SoC, including CPU
topology and PSCI support for enabling CPU cores.
R-Car V4H has 4 Cortex-A76 cores, grouped in 2 clusters.
Based on a patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ccb55458bd87f8ba70d28c61bcc254f22184824c.1668429870.git.geert+renesas@glider.be
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