Searched hist:"62 ff262227a45bf917fe198885ab7aa19be5a01f" (Results 1 – 5 of 5) sorted by relevance
| /linux/arch/riscv/include/asm/ |
| H A D | cpu_ops.h | diff 62ff262227a45bf917fe198885ab7aa19be5a01f Wed Nov 22 00:47:26 CET 2023 Samuel Holland <samuel.holland@sifive.com> riscv: Use the same CPU operations for all CPUs
RISC-V provides no binding (ACPI or DT) to describe per-cpu start/stop
operations, so cpu_set_ops() will always detect the same operations for
every CPU. Replace the cpu_ops array with a single pointer to save space
and reduce boot time.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231121234736.3489608-4-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
|
| /linux/arch/riscv/kernel/ |
| H A D | cpu_ops.c | diff 62ff262227a45bf917fe198885ab7aa19be5a01f Wed Nov 22 00:47:26 CET 2023 Samuel Holland <samuel.holland@sifive.com> riscv: Use the same CPU operations for all CPUs
RISC-V provides no binding (ACPI or DT) to describe per-cpu start/stop
operations, so cpu_set_ops() will always detect the same operations for
every CPU. Replace the cpu_ops array with a single pointer to save space
and reduce boot time.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231121234736.3489608-4-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
|
| H A D | cpu-hotplug.c | diff 62ff262227a45bf917fe198885ab7aa19be5a01f Wed Nov 22 00:47:26 CET 2023 Samuel Holland <samuel.holland@sifive.com> riscv: Use the same CPU operations for all CPUs
RISC-V provides no binding (ACPI or DT) to describe per-cpu start/stop
operations, so cpu_set_ops() will always detect the same operations for
every CPU. Replace the cpu_ops array with a single pointer to save space
and reduce boot time.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231121234736.3489608-4-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
|
| H A D | smp.c | diff 62ff262227a45bf917fe198885ab7aa19be5a01f Wed Nov 22 00:47:26 CET 2023 Samuel Holland <samuel.holland@sifive.com> riscv: Use the same CPU operations for all CPUs
RISC-V provides no binding (ACPI or DT) to describe per-cpu start/stop
operations, so cpu_set_ops() will always detect the same operations for
every CPU. Replace the cpu_ops array with a single pointer to save space
and reduce boot time.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231121234736.3489608-4-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
|
| H A D | smpboot.c | diff 62ff262227a45bf917fe198885ab7aa19be5a01f Wed Nov 22 00:47:26 CET 2023 Samuel Holland <samuel.holland@sifive.com> riscv: Use the same CPU operations for all CPUs
RISC-V provides no binding (ACPI or DT) to describe per-cpu start/stop
operations, so cpu_set_ops() will always detect the same operations for
every CPU. Replace the cpu_ops array with a single pointer to save space
and reduce boot time.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231121234736.3489608-4-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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