Searched hist:"61 fa969f27ec58296544bf94d058f3aa704cb8d9" (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/mips/include/asm/mach-lantiq/falcon/ |
| H A D | falcon_irq.h | diff 61fa969f27ec58296544bf94d058f3aa704cb8d9 Thu Aug 16 13:39:57 CEST 2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: split up IRQ IM ranges
Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/
|
| /linux/arch/mips/include/asm/mach-lantiq/xway/ |
| H A D | lantiq_irq.h | diff 61fa969f27ec58296544bf94d058f3aa704cb8d9 Thu Aug 16 13:39:57 CEST 2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: split up IRQ IM ranges
Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/
|
| /linux/arch/mips/lantiq/ |
| H A D | irq.c | diff 61fa969f27ec58296544bf94d058f3aa704cb8d9 Thu Aug 16 13:39:57 CEST 2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: split up IRQ IM ranges
Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/
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