Searched hist:"53 a848be0a65c6fb105eb5ecb8b8b3edfa0f91ad" (Results 1 – 3 of 3) sorted by relevance
| /linux/Documentation/devicetree/bindings/arm/omap/ |
| H A D | l3-noc.txt | diff 53a848be0a65c6fb105eb5ecb8b8b3edfa0f91ad Thu Apr 10 18:33:13 CEST 2014 Rajendra Nayak <rnayak@ti.com> bus: omap_l3_noc: Add DRA7 interconnect error data
DRA7 is distinctly different from OMAP4 in terms of masters and clock
domain organization. There two main clock domains which is divided as
follows:
<0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain
<0x45000000 0x1000> is clk3
Add all the data needed to handle L3 error handling on DRA7 devices
and mark clk2 as subdomain and provide a compatible flag for
functionality. Other than the data difference the hardware blocks
involved are essentially the same.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: bugfixes and generic improvements, documentation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
|
| /linux/drivers/bus/ |
| H A D | omap_l3_noc.h | diff 53a848be0a65c6fb105eb5ecb8b8b3edfa0f91ad Thu Apr 10 18:33:13 CEST 2014 Rajendra Nayak <rnayak@ti.com> bus: omap_l3_noc: Add DRA7 interconnect error data
DRA7 is distinctly different from OMAP4 in terms of masters and clock
domain organization. There two main clock domains which is divided as
follows:
<0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain
<0x45000000 0x1000> is clk3
Add all the data needed to handle L3 error handling on DRA7 devices
and mark clk2 as subdomain and provide a compatible flag for
functionality. Other than the data difference the hardware blocks
involved are essentially the same.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: bugfixes and generic improvements, documentation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
|
| H A D | omap_l3_noc.c | diff 53a848be0a65c6fb105eb5ecb8b8b3edfa0f91ad Thu Apr 10 18:33:13 CEST 2014 Rajendra Nayak <rnayak@ti.com> bus: omap_l3_noc: Add DRA7 interconnect error data
DRA7 is distinctly different from OMAP4 in terms of masters and clock
domain organization. There two main clock domains which is divided as
follows:
<0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain
<0x45000000 0x1000> is clk3
Add all the data needed to handle L3 error handling on DRA7 devices
and mark clk2 as subdomain and provide a compatible flag for
functionality. Other than the data difference the hardware blocks
involved are essentially the same.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: bugfixes and generic improvements, documentation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
|