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H A D | spi-rockchip.c | diff 5185a81c02d4118b11e6cb7b5fbf6f15ff7aff90 Fri Jul 15 03:30:59 CEST 2016 Brian Norris <briannorris@chromium.org> spi: rockchip: limit transfers to (64K - 1) bytes
The Rockchip SPI controller's length register only supports 16-bits, yielding a maximum length of 64KiB (the CTRLR1 register holds "length - 1"). Trying to transfer more than that (e.g., with a large SPI flash read) will cause the driver to hang.
Now, it seems that while theoretically we should be able to program CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to cause the core to choke, so stick with a maximum of 64K - 1 bytes -- i.e., 0xffff.
Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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