Searched hist:"4 f357f94e13d92e514be291fc71ddf154c3b6c62" (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hip07-d05.dts | 4f357f94e13d92e514be291fc71ddf154c3b6c62 Sat Sep 24 11:14:23 CEST 2016 Kefeng Wang <wangkefeng.wang@huawei.com> arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
Adding initial dt file for Hip07 D05 board, it is with dual socket
and each socket has two SCCLs(supper cpu cluster), one SCCL contains
four clusters and each cluster has quard Cortex-A72.
Since each SCCL has their own DDR controller, it could be treated as
a separate numa node. Thus, there are four numa nodes(one node with
sixteen core) on Hip07 SoC.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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| H A D | Makefile | diff 4f357f94e13d92e514be291fc71ddf154c3b6c62 Sat Sep 24 11:14:23 CEST 2016 Kefeng Wang <wangkefeng.wang@huawei.com> arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
Adding initial dt file for Hip07 D05 board, it is with dual socket
and each socket has two SCCLs(supper cpu cluster), one SCCL contains
four clusters and each cluster has quard Cortex-A72.
Since each SCCL has their own DDR controller, it could be treated as
a separate numa node. Thus, there are four numa nodes(one node with
sixteen core) on Hip07 SoC.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
|
| H A D | hip07.dtsi | 4f357f94e13d92e514be291fc71ddf154c3b6c62 Sat Sep 24 11:14:23 CEST 2016 Kefeng Wang <wangkefeng.wang@huawei.com> arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
Adding initial dt file for Hip07 D05 board, it is with dual socket
and each socket has two SCCLs(supper cpu cluster), one SCCL contains
four clusters and each cluster has quard Cortex-A72.
Since each SCCL has their own DDR controller, it could be treated as
a separate numa node. Thus, there are four numa nodes(one node with
sixteen core) on Hip07 SoC.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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