Searched hist:"4 ee93d80ad73980826d582c7c37caa9597822001" (Results 1 – 5 of 5) sorted by relevance
| /linux/arch/openrisc/mm/ |
| H A D | Makefile | diff 4ee93d80ad73980826d582c7c37caa9597822001 Wed Nov 04 17:26:10 CET 2015 Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de> openrisc: add cacheflush support to fix icache aliasing
On OpenRISC the icache does not snoop data stores. This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory. It supports both
SMP and UP flushing.
This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.
Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| H A D | cache.c | 4ee93d80ad73980826d582c7c37caa9597822001 Wed Nov 04 17:26:10 CET 2015 Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de> openrisc: add cacheflush support to fix icache aliasing
On OpenRISC the icache does not snoop data stores. This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory. It supports both
SMP and UP flushing.
This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.
Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| /linux/arch/openrisc/include/asm/ |
| H A D | cacheflush.h | 4ee93d80ad73980826d582c7c37caa9597822001 Wed Nov 04 17:26:10 CET 2015 Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de> openrisc: add cacheflush support to fix icache aliasing
On OpenRISC the icache does not snoop data stores. This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory. It supports both
SMP and UP flushing.
This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.
Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| H A D | pgtable.h | diff 4ee93d80ad73980826d582c7c37caa9597822001 Wed Nov 04 17:26:10 CET 2015 Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de> openrisc: add cacheflush support to fix icache aliasing
On OpenRISC the icache does not snoop data stores. This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory. It supports both
SMP and UP flushing.
This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.
Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| /linux/arch/openrisc/kernel/ |
| H A D | smp.c | diff 4ee93d80ad73980826d582c7c37caa9597822001 Wed Nov 04 17:26:10 CET 2015 Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de> openrisc: add cacheflush support to fix icache aliasing
On OpenRISC the icache does not snoop data stores. This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory. It supports both
SMP and UP flushing.
This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.
Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
|