Searched hist:"4 c0b6eaf373a5323f03a3a20c42fc435715b073d" (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/net/ethernet/cavium/thunder/ |
| H A D | nic_reg.h | diff 4c0b6eaf373a5323f03a3a20c42fc435715b073d Wed Feb 24 12:10:50 CET 2016 Sunil Goutham <sgoutham@cavium.com> net: thunderx: Fix for Qset error due to CQ full
On Thunderx pass 1.x and pass2 due to a HW errata default CQ
DROP_LEVEL of 0x80 is not sufficient to avoid CQ_WR_FULL Qset
error when packets are being received at >20Mpps resulting in
complete stall of packet reception.
This patch will configure it to 0x100 which is what is expected
by HW on Thunderx. On future passes of thunderx and other chips
HW default/reset value will be 0x100 or higher hence not overwritten.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| H A D | nic.h | diff 4c0b6eaf373a5323f03a3a20c42fc435715b073d Wed Feb 24 12:10:50 CET 2016 Sunil Goutham <sgoutham@cavium.com> net: thunderx: Fix for Qset error due to CQ full
On Thunderx pass 1.x and pass2 due to a HW errata default CQ
DROP_LEVEL of 0x80 is not sufficient to avoid CQ_WR_FULL Qset
error when packets are being received at >20Mpps resulting in
complete stall of packet reception.
This patch will configure it to 0x100 which is what is expected
by HW on Thunderx. On future passes of thunderx and other chips
HW default/reset value will be 0x100 or higher hence not overwritten.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | nic_main.c | diff 4c0b6eaf373a5323f03a3a20c42fc435715b073d Wed Feb 24 12:10:50 CET 2016 Sunil Goutham <sgoutham@cavium.com> net: thunderx: Fix for Qset error due to CQ full
On Thunderx pass 1.x and pass2 due to a HW errata default CQ
DROP_LEVEL of 0x80 is not sufficient to avoid CQ_WR_FULL Qset
error when packets are being received at >20Mpps resulting in
complete stall of packet reception.
This patch will configure it to 0x100 which is what is expected
by HW on Thunderx. On future passes of thunderx and other chips
HW default/reset value will be 0x100 or higher hence not overwritten.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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