Searched hist:"4 bb9ca7ee07455bec0a802ecf0aa5b09496888e2" (Results 1 – 3 of 3) sorted by relevance
/linux/drivers/gpu/drm/i915/gt/ |
H A D | intel_gt_pm_debugfs.c | diff 4bb9ca7ee07455bec0a802ecf0aa5b09496888e2 Mon Nov 14 13:33:48 CET 2022 Badal Nilawar <badal.nilawar@intel.com> drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Add support for C6 residency and C state type for MTL SAMedia. Also add mtl_drpc.
v2: Fixed review comments (Ashutosh) v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R) Remove MTL_CC_SHIFT (Ashutosh) Adapt to RC6 residency register code refactor (Jani N) v4: Move MTL branch to top in drpc_show v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh) v6: Add MISSING_CASE for gt_core_status switch statement (Rodrigo) Change state name for MTL_CC0 to C0 (from "on") (Rodrigo) v7: Change state name for MTL_CC0 to RC0 (Rodrigo)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221114123348.3474216-6-badal.nilawar@intel.com
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H A D | intel_gt_regs.h | diff 4bb9ca7ee07455bec0a802ecf0aa5b09496888e2 Mon Nov 14 13:33:48 CET 2022 Badal Nilawar <badal.nilawar@intel.com> drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Add support for C6 residency and C state type for MTL SAMedia. Also add mtl_drpc.
v2: Fixed review comments (Ashutosh) v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R) Remove MTL_CC_SHIFT (Ashutosh) Adapt to RC6 residency register code refactor (Jani N) v4: Move MTL branch to top in drpc_show v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh) v6: Add MISSING_CASE for gt_core_status switch statement (Rodrigo) Change state name for MTL_CC0 to C0 (from "on") (Rodrigo) v7: Change state name for MTL_CC0 to RC0 (Rodrigo)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221114123348.3474216-6-badal.nilawar@intel.com
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H A D | intel_rc6.c | diff 4bb9ca7ee07455bec0a802ecf0aa5b09496888e2 Mon Nov 14 13:33:48 CET 2022 Badal Nilawar <badal.nilawar@intel.com> drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Add support for C6 residency and C state type for MTL SAMedia. Also add mtl_drpc.
v2: Fixed review comments (Ashutosh) v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R) Remove MTL_CC_SHIFT (Ashutosh) Adapt to RC6 residency register code refactor (Jani N) v4: Move MTL branch to top in drpc_show v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh) v6: Add MISSING_CASE for gt_core_status switch statement (Rodrigo) Change state name for MTL_CC0 to C0 (from "on") (Rodrigo) v7: Change state name for MTL_CC0 to RC0 (Rodrigo)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221114123348.3474216-6-badal.nilawar@intel.com
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