Searched hist:"46 a57afdd70c17cf15b2077c5ea611913f80f85f" (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/clk/st/ |
| H A D | clkgen.h | diff 46a57afdd70c17cf15b2077c5ea611913f80f85f Wed Oct 07 11:08:57 CEST 2015 Gabriel Fernandez <gabriel.fernandez@linaro.org> drivers: clk: st: PLL rate change implementation for DVFS
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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| H A D | clkgen-mux.c | diff 46a57afdd70c17cf15b2077c5ea611913f80f85f Wed Oct 07 11:08:57 CEST 2015 Gabriel Fernandez <gabriel.fernandez@linaro.org> drivers: clk: st: PLL rate change implementation for DVFS
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
| H A D | clkgen-pll.c | diff 46a57afdd70c17cf15b2077c5ea611913f80f85f Wed Oct 07 11:08:57 CEST 2015 Gabriel Fernandez <gabriel.fernandez@linaro.org> drivers: clk: st: PLL rate change implementation for DVFS
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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