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| H A D | Kconfig | diff 4562fa4c86c92a2df635fe0697c9e06379738741 Wed Dec 11 03:53:36 CET 2019 Anson Huang <Anson.Huang@nxp.com> ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D
ARM_ERRATA_814220 has below description:
The v7 ARM states that all cache and branch predictor maintenance
operations that do not specify an address execute, relative to
each other, in program order.
However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation.
This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
r0p4, r0p5.
i.MX6UL and i.MX7D have Cortex-A7 r0p5 inside, need to enable
ARM_ERRATA_814220 for proper workaround.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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