Searched hist:"4553474 d977d1ee8a81067cfbc588f1df84ce3e9" (Results 1 – 5 of 5) sorted by relevance
| /linux/arch/openrisc/kernel/ |
| H A D | sync-timer.c | 4553474d977d1ee8a81067cfbc588f1df84ce3e9 Thu Jul 06 23:06:30 CEST 2017 Stafford Horne <shorne@gmail.com> openrisc: add tick timer multi-core sync logic
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.
This synchronization routine heavily borrows from mips implementation that
does something similar.
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| H A D | Makefile | diff 4553474d977d1ee8a81067cfbc588f1df84ce3e9 Thu Jul 06 23:06:30 CEST 2017 Stafford Horne <shorne@gmail.com> openrisc: add tick timer multi-core sync logic
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.
This synchronization routine heavily borrows from mips implementation that
does something similar.
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| H A D | smp.c | diff 4553474d977d1ee8a81067cfbc588f1df84ce3e9 Thu Jul 06 23:06:30 CEST 2017 Stafford Horne <shorne@gmail.com> openrisc: add tick timer multi-core sync logic
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.
This synchronization routine heavily borrows from mips implementation that
does something similar.
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| H A D | time.c | diff 4553474d977d1ee8a81067cfbc588f1df84ce3e9 Thu Jul 06 23:06:30 CEST 2017 Stafford Horne <shorne@gmail.com> openrisc: add tick timer multi-core sync logic
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.
This synchronization routine heavily borrows from mips implementation that
does something similar.
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| /linux/arch/openrisc/include/asm/ |
| H A D | time.h | diff 4553474d977d1ee8a81067cfbc588f1df84ce3e9 Thu Jul 06 23:06:30 CEST 2017 Stafford Horne <shorne@gmail.com> openrisc: add tick timer multi-core sync logic
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.
This synchronization routine heavily borrows from mips implementation that
does something similar.
Signed-off-by: Stafford Horne <shorne@gmail.com>
|