Searched hist:"44 d30d622821d3bf7fa74b62e2ea62bde314ec1b" (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/phy/cadence/ |
| H A D | Makefile | diff 44d30d622821d3bf7fa74b62e2ea62bde314ec1b Mon Nov 12 17:42:16 CET 2018 Alan Douglas <adouglas@cadence.com> phy: cadence: Add driver for Sierra PHY
Add a Sierra PHY driver with PCIe and USB support.
The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.
There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself. Additionally there are
resets for each PHY lane.
The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.
The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required) for each lane
group, and then enable the PHY. Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
| H A D | Kconfig | diff 44d30d622821d3bf7fa74b62e2ea62bde314ec1b Mon Nov 12 17:42:16 CET 2018 Alan Douglas <adouglas@cadence.com> phy: cadence: Add driver for Sierra PHY
Add a Sierra PHY driver with PCIe and USB support.
The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.
There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself. Additionally there are
resets for each PHY lane.
The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.
The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required) for each lane
group, and then enable the PHY. Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
| H A D | phy-cadence-sierra.c | 44d30d622821d3bf7fa74b62e2ea62bde314ec1b Mon Nov 12 17:42:16 CET 2018 Alan Douglas <adouglas@cadence.com> phy: cadence: Add driver for Sierra PHY
Add a Sierra PHY driver with PCIe and USB support.
The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.
There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself. Additionally there are
resets for each PHY lane.
The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.
The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required) for each lane
group, and then enable the PHY. Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|