Searched hist:"3 e4947acad32e6abf1ef3259a42fb4d690e4819a" (Results 1 – 2 of 2) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| H A D | imx8mm-clock.h | diff 3e4947acad32e6abf1ef3259a42fb4d690e4819a Wed Oct 16 13:57:39 CEST 2019 Leonard Crestez <leonard.crestez@nxp.com> clk: imx8mm: Define gates for pll1/2 fixed dividers
On imx8mm there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.
Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
| /linux/drivers/clk/imx/ |
| H A D | clk-imx8mm.c | diff 3e4947acad32e6abf1ef3259a42fb4d690e4819a Wed Oct 16 13:57:39 CEST 2019 Leonard Crestez <leonard.crestez@nxp.com> clk: imx8mm: Define gates for pll1/2 fixed dividers
On imx8mm there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.
Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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